參數(shù)資料
型號： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁數(shù)： 22/92頁
文件大?。?/td> 1401K
代理商： 84220
22
MD400177/B
84220
2.10.5 Fiber Interface Disable
The Fiber Interface will be disabled if the SD/FXEN pin is
tied to GND. Disabling the Fiber Interface automatically
enables the TP interface.
2.10.6 Far End Fault
Each channel has the Far End Fault capability, referred to
as FEF defined in IEEE 802.3 specifications. FEF is a
method by which the Fiber Interface can signal a fault to a
remote device by transmitting an idle pattern consisting of
84 ‘1’s followed by a single ‘0’ repeatedly (idle period
normally has all 1’s). FEF was specified in IEEE 802.3
because FX lacks the AutoNegotiation capability to signal
a remote fault to another station.
FEF can only be made operational only when the Fiber
Interface is enabled. In the device default state with the
Fiber Interface enabled, FEF is disabled, but it can be
enabled by setting the FEF select bit in the MI serial port
Global Configuration register. When FEF is enabled, (1) a
‘0’ is transmitted after each group of 84 ‘1’s repeatedly
during idle if the SD/FXEN pin is deasserted, and (2) if an
FEF stream is detected by the receiver for 3 consecutive
intervals, the remote fault bit is set in the MI serial port
Status register and the LED0 output pin is asserted.
2.11 COLLISION
2.11.1 100 Mbps
Collision occurs whenever transmit and receive occur
simultaneously while the device is in Half Duplex. Collision
is sensed whenever there is simulaneous transmission
(packet transmission on TPOP/N) and reception (non idle
symbols detected on receive input). When collision is
detected:
The COL output is asserted.
TP data continues to be transmitted on twisted pair
outputs.
TP data continues to be received on twisted pair inputs.
Internal CRS loopback is disabled.
Once collision starts, CRS is asserted and stays asserted
until the receive and transmit packets that caused the
collision are terminated.
The collision function is disabled if the device is in the Full
Duplex mode, is in the Link Fail state, or if the device is in
the diagnostic loopback mode.
2.11.2 10 Mbps
Collision in 10 Mbps mode is identical to the 100 Mbps
mode, except:
Reception is detemined by the 10 Mbps squelch
criteria.
RXD[3:0] outputs are forced to all 0's.
Collision is asserted when the SQE test is performed.
Collision is asserted when the jabber condition has
been detected.
2.11.3 Collision Test
The controller interface collision signal, COL, can be
tested by setting the collision test register bit in the MI
serial port Control register. When this bit is set, TXEN is
looped back onto COL and the TP outputs are disabled.
2.11.4 Collision Indication
Collision can be programmed to appear on the LED2 pin
by appropriately setting the LED definition bits in the MI
serial port Global Configuration register. The LED
DRIVERS Section describes the programmable LED
definition bit settings. When the LED2 pin is programmed
to be a collision detect output, the pin is asserted low for
100 mS every time a collision occurs.
2.12 START OF PACKET
2.12.1 100 Mbps
Start of packet for 100 Mbps mode is indicated by a
unique Start of Stream Delimiter (SSD). The SSD pattern
consists of the two /J/K/ 5B symbols inserted at the
beginning of the packet in place of the first two preamble
symbols, as defined in IEEE 802.3 Clause 24 and shown
in Table 1 and Figure 2.
The transmit SSD is generated by the 4B5B encoder and
the /J/K/ symbols are inserted by the 4B5B encoder at the
beginning of the transmit data packet in place of the first
two 5B symbols of the preamble, as shown in Figure 2.
The receive pattern is detected by the 4B5B decoder by
examining groups of 10 consecutive code bits (two 5B
words) from the descrambler. Between packets, the
receiver will be detecting the idle pattern, which is 5B /I/
symbols. While in the idle state, CRS and RXDV are
deasserted.
If the receiver is in the idle state and 10 consecutive code
bits from the receiver consist of the /J/K/ symbols, the
start of packet is detected, data reception is begun, CRS
and RXDV are asserted, and /5/5/ symbols are substituted
in place of the /J/K/ symbols.
If the receiver is in the idle state and 10 consecutive code
bits from the receiver consist of a pattern that is neither /I/
I/ nor /J/K/ symbols but contains at least 2 non-contiguous
相關PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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