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參數(shù)資料
| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 55/92頁 |
| 文件大小： | 1401K |
| 代理商： | 84220 |
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MD400177/B
84220
55
For some particular types of repeaters, it may be
desirable to either enable or disable AutoNegotiation,
force Half Duplex operation, and enable either 100 Mbps
or 10 Mbps operation. All of these modes can be
configured by setting the appropriate bits in the MI serial
port Control register.
4.9.3 Clocks
Normally, transmit data sent over the MII/RMII/FBI is
clocked into the 84220 by the rising edge of the output
clock TXCLK. It may be desireable or necessary in some
repeater applications to clock in transmit data from a
master clock from the repeater core. This would require
that transmit data be clocked in on the edge of an input
clock. An input clock is available for clocking in data on
TXD by the rising edge on the CLKIN pin. Notice from the
timing diagrams that CLKIN generates TXCLK, and TXD
data is clocked in on TXCLK edges. This means that TXD
data is also clocked in on the CLKIN edge as well. Thus,
an external clock driving the CLKIN input can also be
used as the clock for TXD.
4.10 SERIAL PORT
4.10.1 General
The 84220 has a MI serial port to set all of the devices's
configuration inputs and read out the status outputs. Any
external device that has an IEEE 802.3 compliant MI
interface can connect directly to the 84220 without any
glue logic, as shown in Figure 12 and Figure 13.
As described earlier, the MI serial port consists of six
lines: MDC, MDIO, MDINT and PHYAD[4:2]. However,
only 2 lines, MDC and MDIO, are needed to shift data in
and out.
MDINT is used as an interrupt output indicator, as
described in Section 4.10.2, Polling vs. Interrupt.
PHYAD[4:2] define the three most significant bits of the
PHY address, as described in the Serial Port Addressing
Section.
4.10.2 Polling vs. Interrupt
The status output bits can be monitored by either polling
the serial port or with the interrupt output.
If polling is used, the registers can be read at regular
intervals and the status bits can be checked against their
previous values to determine any changes. To make
polling simpler, all the registers can be accessed in a
single read or write cycle by setting the register address
bits REGAD[4:0] to 11111 and adding enough clocks to
read out all the bits, provided the multiple register access
feature has been enabled.
The interrupt feature offers the ability to detect changes in
the status output bits without register polling. Assertion of
the interrupt output indicates that one or more of the
status bits has changed since the last read cycle. There
are three interrupt output indicators on the 84220:
MDINT pin.
Interrupt pulse on MDIO.
INT bit in the MI serial port Channel Status Output
register.
These interrupt signals can be used by an external device
to initiate a read cycle. When an interrupt is detected, the
individual registers (or multiple registers) can be read out
and the status bits compared against their previous
values to determine any changes. After the interrupt bits
have been read out, the interrupt signals are
automatically deasserted.
A quick way to determine which status bit(s) changed in
which Channel Status Output register(s) is to do a
register read by setting the PHYAD[4:2] (frame field bits)
equal to the PHYAD[4:2] (pins) and setting REGAD to
11110. The accessed register will not be determined by
REGAD anymore. Instead, the register accessed is the
Channel Status Output Register where the interrupt bit
has changed. The channel address of this Channel
Status Output Register can be found from the CHAD[1:0]
bits in this register.
A mask register bit exists for every status output bit in the
MI serial port. The Global Interrupt Mask register allows
the interrupt bits to be individually programmed for each
application.
4.10.3 Multiple Register Access
If the MI serial port needs to be constantly polled in order
to monitor changes in status output bits, or if it is desired
that all registers be read or written in a single serial port
access cycle, then multiple register access mode can be
used. Multiple register access allows all 84220 registers
to be read in a single MI serial port access cycle. When
multiple register access is enabled, all registers are read/
written when the register address REGAD[4:0]=11111.
This eliminates the need to read or write registers
individually. Multiple register access mode is normally
disabled, but can be enabled by setting the multiple
register access enable bit in the MI serial port Global
Configuration register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
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| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
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