參數(shù)資料
型號(hào)： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 26/92頁(yè)
文件大?。?/td> 1401K
代理商： 84220
26
MD400177/B
84220
device should be configured according to the priority
resolution algorithm defined in IEEE 802.3 Clause 28.
Once the negotiation process is completed, the 84220
then configures itself for either 10 or 100 Mbps mode and
either Full or Half Duplex modes (depending on the
outcome of the negotiation process), and it switches to
either the 100Base-TX or 10Base-T link integrity
algorithms (depending on which mode was enabled by
AutoNegotiation). Refer to IEEE 802.3 Clause 28 for more
details.
2.14.5 AutoNegotiation Outcome Indication
The outcome or result of the AutoNegotiation process is
stored in the speed detect and duplex detect bits in the MI
serial port Status Output register.
2.14.6 AutoNegotiation Status
The status of the AutoNegotiation process can be
monitored by reading the AutoNegotiation Acknow-
ledgement Bit in the MI serial port Status register.
2.14.7 AutoNegotiation Enable
The AutoNegotiation algorithm can be enabled (or
restarted) by setting the AutoNegotiation enable bit in the
MI serial port Control register or by asserting the ANEG
pin. The AutoNegotiatiopn enable bit and ANEG pin both
have to be high to enable AutoNegotiation. When the
AutoNegotiation algorithm is enabled, the device halts all
transmissions including link pulses for 1200-1500 mS,
enters the Link Fail state, and restarts the negotiation
process. When the AutoNegotiation algorithm is disabled,
the selection of 100 Mbps or 10 Mbps mode is determined
by the speed select bit in the MI serial port Control
register, and the selection of Half or Full Duplex is
determined by the duplex select bit in the MI serial port
Control register.
2.14.8 AutoNegotiation Reset
The AutoNegotiation algorithm can be initiated at any time
by setting the AutoNegotiation reset bit in the MI serial
port Control register.
2.14.9 Link Indication
Receive link detect activity can be monitored through the
link detect bit in the MI serial port Status and Status
Output registers or it can also be programmed to appear
on LED status pins by appropriately setting the
programmable LED select bits in the MI serial port
Configuration 2 register as shown in Table 4. Whenever
the LED Status pins are programmed to be a link detect
output, these pins are asserted low whenever the device is
in the Link Pass state.
2.14.10 Link Disable
The link integrity function can be disabled by setting the
link disable bit in the MI serial port Configuration 1
register. When the link integrity function is disabled, the
device is forced into the Link Pass state, configures itself
for Half/Full Duplex based on the value of the duplex bit in
the MI serial port Control register, configures itself for 100/
10 Mbps operation based on the values of the speed bit in
the MI serial port Control register, and continues to
transmit NLP’s or TX idle patterns, depending on whether
the device is in 10 or 100 Mbps mode.
2.15 JABBER
2.15.1 100 Mbps
The jabber function is disabled in the 100 Mbps mode.
2.15.2 10 Mbps
A jabber condition occurs when the transmit packet
exceeds a predetermined length. When jabber is
detected, the TP transmit outputs are forced to the idle
state, collision is asserted, and jabber register bits in the
MI serial port Status and Channel Status Output registers
are set.
2.15.3 Jabber Disable
The jabber function can be disabled by setting the jabber
disable bit in the MI serial port Global Configuration
register.
2.16 RECEIVE POLARITY CORRECTION
2.16.1 100 Mbps
No polarity detection or correction is needed in 100 Mbps
mode.
2.16.2 10 Mbps
The polarity of the signal on the TP receive input is
continuously monitored. If one SOI pulse indicates
incorrect polarity on the TP receive input, the polarity is
internally determined to be incorrect, and the reverse
polarity bit is set in the MI serial port Channel Status
Output register.
The 84220 will automatically correct for the reverse
polarity condition provided that the autopolarity feature is
not disabled.
相關(guān)PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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