參數(shù)資料
型號: 84220
廠商: LSI Corporation
英文描述: Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device (Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications)(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器))
中文描述: 四100BaseTX/100BaseFX/10BaseT物理層裝置(高度集成的以太網(wǎng)收發(fā)器,雙絞線和光纖以太網(wǎng)的應用)(四通道100BaseTX/100BaseFX/10BaseT物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器) )
文件頁數(shù): 57/92頁
文件大?。?/td> 1401K
代理商: 84220
MD400177/B
84220
57
4.17 5V COMPATIBLE I/O OPERATION
The input and output pins of the 84220 are tolerant of
signal levels up to a maximum of 5.5V (including
overshoot etc.). This allows the transceiver to be
operated with 5V controllers that have TTL I/O
characteristics (0.8 to 2.0V Input levels) without the use of
levelshifters or other interfaces.
Controllers and other system components may be
operate with 5V supplies and all inter-chip signals may be
connected directly to the 84220. All required external
logic levels must retain TTL compatability since the 84220
outputs are not guaranteed to achieve higher than 2.3V
with a load of 10ma. However, the inputs of the 84220 will
tolearte TTL or CMOS logic levels being driven into the
device.
This should make replacement of the Physical Layer
transceivers in existing designs quite simple since any 5V
devices do not need to be changed.
4.18 POWER SUPPLY DECOUPLING
There are 18 VDD's and 19 GND's on the 84220.
All VDD's on each individual side should be connected
together (grouped) and tied to a power plane, as close as
possible to the 84220 supply pins. If the VDD's vary in
potential by even a small amount, noise and latchup can
result. The 84220 VDD pins should be kept to within 50
mV of each other.
All GND's should be connected as close as possible to
the device with a large ground plane. If the GND's vary in
potential by even a small amount, noise and latchup can
result. The GND pins should be kept to within 50 mV of
each other.
A 0.01-0.1uF decoupling capacitor should be connected
between the VDD group and GND on each of the 4 sides
of the 84220 as close as possible to the device pins,
preferably within 0.5 in. The value should be chosen
depending on whether the noise from VDD-GND is high
or low frequency. A conservative approach would be to
use two decoupling capacitors on each side, one 0.1uf for
low frequencys, and one 0.001 uf for high frequency noise
on the power supply.
The VDD connection to the transmit transformer center
tap shown in Figures 12 and 13 must be well decoupled in
order to minimize common mode noise injection from the
supply into the twisted pair cable. It is recommended that
a 0.01 uF decoupling capacitor be placed between the
transformer center tap VDD connection and the 84220
GND plane. This decoupling capacitor should be
physically placed as close as possible to the transformer
center tap, preferably within 0.5 in.
The PCB layout and power supply decoupling discussed
above should provide sufficient decoupling to achieve the
following when measured at the device:
(1) the resultant AC noise voltage measured across
each VDD/GND set should be less than 100 mVpp,
(2) all VDD’s should be within 50 mVpp of each other,
and
(3) all GND’s should be within 50 mVpp of each other.
相關PDF資料
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84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
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