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參數(shù)資料
| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 20/92頁 |
| 文件大小： | 1401K |
| 代理商： | 84220 |
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MD400177/B
84220
2.8.5 TP Output Disable
The TP transmitter can be disabled by setting the output
disable bit in the MI serial port Channel Configuration
register. When the transmitter is disabled, the TP transmit
outputs are placed in the high impedance state and TXEN
to CRS loopback will be disabled.
2.8.6 STP (150 Ohm) Cable Mode
The transmitter can be configured to drive 150 ohm
shielded twisted pair cable. When STP mode is enabled,
the output current is automatically adjusted to comply with
IEEE 802.3 levels. The STP mode can be selected by
appropriately setting the cable type select bit in the MI
serial port Channel Configuration register.
2.9 TWISTED PAIR RECEIVER
2.9.1 Receiver - 100 Mbps
The TP receiver detects input signals from the twisted pair
input and converts it to a digital data bit stream ready for
clock and data recovery. The receiver can reliably detect
data from a 100Base-TX compliant transmitter that has
been passed through 0-100 meters of 100 Ohm category
5 UTP or 150 Ohm STP
The 100 Mbps receiver consists of an adaptive equalizer,
baseline wander correction circuit, comparators, and MLT-
3 decoder. The TP inputs first go to an adaptive equalizer.
The adaptive equalizer compensates for the low pass
characteristic of the cable, and it has the ability to adapt
and compensate for 0-100 meters of category 5, 100 Ohm
UTP or 150 Ohm STP twisted pair cable. The baseline
wander correction circuit restores the DC component of
the input waveform that was removed by external
transformers. The comparators convert the equalized
signal back to digital levels and are used to qualify the
data with the squelch circuit. The MLT-3 decoder takes the
three level MLT-3 digital data from the comparators and
converts it back to normal digital data to be used for clock
and data recovery.
2.9.2 Receiver - 10 Mbps
The 10 Mbps mode receiver is much simpler than the 100
Mbps mode receiver and is identical to the 100 Mbps
receiver except:
The adaptive equalizer is disabled and bypassed.
The baseline wander correction circuit is disabled.
The 10 Mbps receiver is able to detect input signals
from the twisted pair cable that are within the template
specified in IEEE 802.3 Clause 14 and shown in Figure
5.
The output of the squelch comparator is used for
squelch, link pulse detect, SOI detect, reverse polarity
detect.
The data comparator is a zero crossing comparator
whose output is used for clock and data recovery.
2.9.3 Squelch - 100 Mbps
The squelch block determines whether the input contains
valid data. The 100 Mbps TX squelch is one of the criteria
used to determine link intergrity. The squelch
comparators compare the TX inputs against fixed positive
and negative thresholds, called squelch levels.
The output from the squelch comparator goes to a digital
squelch circuit, which determines whether the receive
input data on that channel is valid. If the data is invalid,
the receiver is in the squelched state. If the input voltage
exceeds the squelch levels at least four times with
alternating polarity within a 10 uS interval, the data is
considered to be valid by the squelch circuit and the
receiver now enters into the unsquelch state.
In the unsquelch state, the receive threshold level is
reduced by approximately 30% for noise immunity
reasons and is called the unsquelch level. When the
receiver is in the unsquelch state the input signal is
considered valid.
The device stays in the unsquelch state until loss of data
is detected. Loss of data is detected if no alternating
polarity unsquelch transitions are detected during any
10 uS interval. When the loss of data is detected, the
receive squelch level is re-established.
2.9.4 Squelch - 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical
to the 100 Mbps mode, except:
The 10 Mbps squelch algorithm is not used for link
integrity, but to sense the beginning of a packet.
The receiver goes into the unsquelch state if the input
voltage exceeds the squelch levels for three bit times
with alternating polarity within a 50-250 nS interval.
The receiver goes into the squelch state when SOI is
detected.
Unsquelch detection has no affect on link integrity, link
pulses are used for that in 10 Mbps mode.
Start of packet is determined when the receiver goes
into the unsquelch state and CRS is asserted.
The receiver meets the squelch requirements defined in
IEEE 802.3 Clause 14.
2.9.5 Receive Level Adjust
The receiver squelch and unsquelch levels can be
lowered by 4.5 dB by setting the receive level adjust bit in
the MI serial port Channel Configuration register. By
setting this bit, the device can support cable lengths
exceeding 100 meters.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
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