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參數(shù)資料
| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 28/92頁 |
| 文件大?。?/td> | 1401K |
| 代理商： | 84220 |
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MD400177/B
84220
The internal CRS loopback can be disabled by setting the
TXEN to CRS loopback disable bit in the MI serial port
Channel Configuration register. When this bit is set, TXEN
is no longer looped back to CRS.
2.19.2 Diagnostic Loopback
A diagnostic loopback mode can also be selected by
setting the loopback bit in the MI serial port Control
register. When diagnostic loopback is enabled, TXD[3:0]
data is looped back onto RXD[3:0], TXEN is looped back
onto CRS, RXDV operates normally, the TP receive and
transmit paths are disabled, the transmit link pulses are
halted, and the Half/Full Duplex modes do not change.
Diagnostic loopback mode can not be enabled when the
FBI interface is selected.
2.20 AUTOMATIC JAM
2.20.1 100 Mbps
The 84220 has an automatic JAM feature which will cause
the device to automatically transmit a JAM packet if
receive activity is detected. If automatic JAM is enabled,
the following JAM packet will be transmitted on TPOP/N
when the JAM pin is asserted active low and receive
activity is detected on TP inputs (expressed in 5B code
words):
/J/K/5/5/5/5/5/5/5/5/5/5/5/5/5/D/H/H/H/H/H/H/H/H/T/R/.
2.20.2 Automatic Jam - 10 Mbps
The JAM feature for 10 Mbps mode is identical to 100
Mbps mode, except the JAM packet transmitted on TPO+
is composed of a standard 56 bit preamble followed by
SFD, followed by 32 bits of alternating 1,0 pattern, as
shown in Figure 2.
2.21 RESET
The 84220 is reset when either:
(1) VDD is applied to the device,
(2) the reset bit is set in the MI serial port Control
register, or
(3) the RESET pin is asserted active low.
When the reset is initiated by either (1) or (2), an internal
power-on reset pulse is generated which resets all internal
circuits, forces the MI serial port bits to their default values,
and latches in new values for the MI address. After the
power-on reset pulse has finished, the reset bit in the MI
serial port Control register is cleared and the device is
ready for normal operation. The device is guaranteed to be
ready for normal operation 50 mS after the reset was
initiated.
When the reset is initiated by (3), the identical procedure
takes place as in (1) and (2), except the device stays in
reset until the RESET pin is deasserted high.
2.22 POWERDOWN
The 84220 can be powered down by setting the
powerdown bit in the MI serial port Control register. In
powerdown mode, the TP outputs are in high impedance
state, all functions are disabled except the MI serial port,
and the power consumption is reduced to a minimum.
The device will be ready for normal operation 50 mS after
powerdown is deasserted.
2.23 CLOCK
The 84220 requires a 25 MHz reference frequency for
internal signal generation in MII mode, and 50 MHz in
RMII mode. This reference frequency must be applied to
the CLKIN pin.
2.24 LED DRIVERS
The LED[3:0] outputs can drive LED’s tied to either VDD
or GND. The LED definitions assume that the LED
outputs are active low. If the LED Anodes are tied to the
positive power supply (through limiting resistors), the LED
will indicate the event as shown in Table 5. If the LED
Cathodes are tied to ground and the Anodes to the 84220
Driver
output,
they
will
complementary events.
indicate
the
respective
The LED[3:0] outputs can also drive other digital inputs.
The LED[3:0] outputs can be programmed to indicate
eight specific sets of events by appropriately setting the
LED definition bits in the MI serial port Global
Configuration register. The default functions for LED[3:0]
are determined by the LED default pin, LEDDEF If
LEDDEF = 0, the LED default functions for LED[3:0] are
Link 100, Activity, Full Duplex, and Link 10, respectively. If
LEDDEF = 1, the LED functions for LED [3:0] are forced to
Link + Activity, Collision, Full Duplex, and 10/100 Mbps
respectively. Table 5 defines the LED functions. Table 6
defines the LED events.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
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