![](http://datasheet.mmic.net.cn/230000/79RC32438-200BB_datasheet_15568909/79RC32438-200BB_514.png)
IDT EJTAG System
Hardware Breakpoints
79RC32438 User Reference Manual
20 - 48
November 4, 2002
Notes
Data Breakpoint Address n (DBAn) Register
Compliance Level
: Required with data breakpoint n, optional otherwise.
The Data Breakpoint Address n (DBAn) register has the address used in the condition for data break-
point n. This register is located at drseg offset 0x2100 + 0x100 * n. Figure 20.15 shows the format of the
DBAn register and Table 20.36 describes the DBAn register field.
Figure 20.15 DBAn Register Format
NoSV-
match
29
Indicates if a value compare on a store is
supported in data breakpoints:
0:
Data value and address in condition
on store
1:
Address compare only in condition on
store
R
Preset
Required
NoLVmatch
28
Indicates if a value compare on a load is
supported in data breakpoints:
0:
Data value and address in condition
on load
1:
Address compare only in condition on
load
R
Preset
Required
BCN
27:24
Number of data breakpoints implemented:
0:
Reserved
1-15:Number of data breakpoints
R
Preset
Required
BS[14:0]
14:0
Break Status (BS) bit for breakpoint n is at
BS[n], where n is 0 to 14. The bit is set to 1
when the condition for its corresponding
breakpoint has matched.
The number of BS bits implemented corre-
sponds to the number of breakpoints indi-
cated by the BCN bit.
Debug software is expected to clear the
bits before use, since these are not cleared
by reset.
Bits not implemented are read-only (R) and
read as zeros.
R/W0
Undefined
Required for
bits at imple-
mented
breakpoints,
other bits not
implemented
0
MSB:31,
23:15
Must be written as zeros; return zeros on
read.
0
0
Reserved
31
0
DBAn
Fields
Description
Read/
Write
Reset
State
Compli-
ance
Name
Bit
DBA
MSB:0
Data breakpoint address for condition.
R/W
Undefined
Required
Table 20.36 DBAn Register Field Description
Fields
Description
Read/
Write
Reset
State
Compli-
ance
Name
Bit
Table 20.35 DBS Register Field Description (Part 2 of 2)