![](http://datasheet.mmic.net.cn/230000/79RC32438-200BB_datasheet_15568909/79RC32438-200BB_358.png)
IDT Ethernet Interfaces
Ethernet MII Management Interface
79RC32438 User Reference Manual
11 - 30
November 4, 2002
Notes
Ethernet MII Management Interface
The MII management interface provides a simple serial interface for controlling PHYs and for gathering
status from PHYs. Both Ethernet interfaces share a single MII management interface. The interface
consists of two pins for reading and writing registers in a PHY:
Clock pin (MIIMDC)
Bidirectional data pin (MIIDIO)
The clock for the management interface is generated by the CPU core and driven on the MIIMDC pin.
The clock frequency driven on this pin is based on the Ethernet management clock generated by the
Ethernet clock prescalar. The Ethernet clock prescalar value should be selected such that the minimum
high and low times for the MIIMDC pin are at least 160 ns, and the minimum period is 400 ns.
A PHY register is read by first writing the desired PHY address into the PHY address (PHYADDR) field
of the MII management address (MIIMADDR) register and writing the desired register address in the
register address (REGADDR) field of the MIIMADDR register. One of two operations can then be selected:
Setting the read (RD) bit in the MII management command (MIICMD) register causes a single read
operation to be performed.
Setting the scan (SCN) bit in the MIICMD register causes repeated reads to be performed from the
selected PHY register.
Once the read data not valid (NV) bit in the MII management indicators register (MIIMIND) is cleared to
0, the value read from the selected PHY register may be read from the MII management read data register
(MIIMRDD) by the CPU core.
A PHY register may be written by writing the desired PHY address into the PHY address (PHYADDR)
field of the MIIMADDR register, and then writing the data to the MII management write data (MIIWTD)
register. A side effect of writing into the MIIWTD register is that a write is performed by the MII management
interface to the selected PHY register. The PHY write operation is completed when the busy (BSY) bit in the
MIIMIND register is cleared.
MII Management Configuration Register
Figure 11.29 MII Management Configuration Register (MIIMCFG)
RSV
Description:
Reserved.
Any value may be written to this field.
Initial Value:
Undefined
Read Value:
Previous value written
Write Effect:
Modify value
MIIMCFG
0
15
0
2
R
1
0
11
RSV
2
16
31
16
0