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IDT PCI Bus Interface
PCI Configuration Registers
79RC32438 User Reference Manual
10 - 59
November 4, 2002
Notes
PCI Base Address [0|1|2|3] Mapping Register
Figure 10.49 PCI Base Address [0|1|2|3] Mapping Register (PBA[0|1|2|3]M)
Read Value:
Previous value written
Write Effect:
Modify value
MRM
Description:
Memory Read Multiple Prefetching Behavior.
This bit controls the behavior of PCI memory
read multiple transactions on the local bus.
0x0 - Conservative Prefetching. Prefetch a 16 word burst from local address space whenever
there are less than 8 words in the PCI target output FIFO.
0x1 - Aggressive Prefetching. Keep prefetching 16 word bursts from local address space as long
as room exists for them in the PCI target output FIFO.
Initial Value:
0x0
Read Value:
Previous value written
Write Effect:
Modify value
TRP
Description:
Target Read Priority.
When this bit is set, PCI target read transactions that map to the
RC32438’s local address space using the corresponding base address are given priority over
posted writes in the PCI target input buffer. When this bit is set, PCI transaction ordering con-
straints are violated. For more information, see section “Transaction Ordering” on page 10-39.
Warning: setting this bit will violate the PCI 2.2 specification since read transactions will
be completed before posted write transactions.
Initial Value:
0x0
Read Value:
Previous value written
Write Effect:
Modify value
MADDR
Description:
Mapping Address.
This field contains the local base address for PCI transactions mapped to
the local bus through the PBAx register. PCI transaction address bits 31 through the value of the
SIZE field in the PBAxC register are replaced by corresponding bits in this field for PCI transac-
tions that map to the local bus through the PBAx register.
Initial Value:
0x0
Read Value:
Previous value written
Write Effect:
Modify value
PBA[0|1|2|3]M
0
31
24
MADDR
0
8