IDT MIPS32 4Kc Processor Core
CP0 Registers
79RC32438 User Reference Manual
2 - 57
November 4, 2002
Notes
Random Register (CP0 Register 1, Select 0)
The Random register is a read-only register whose value is used to index the TLB during a TLBWR
instruction. The width of the Random field is calculated in the same manner as that described for the Index
register above.
The value of the register varies between an upper and lower bound as follow:
A lower bound is set by the number of TLB entries reserved for exclusive use by the operating sys-
tem (the contents of the Wired register). The entry indexed by the Wired register is the first entry
available to be written by a TLB Write Random operation.
An upper bound is set by the total number of TLB entries minus 1.
The Random register is decremented by one almost every clock wrapping after the value in the Wired
register is reached. To enhance the level of randomness and reduce the possibility of a live lock condition,
an LFSR register is used that prevents the decrement pseudo-randomly.
The processor initializes the Random register to the upper bound on a Reset exception and when the
Wired register is written.
This register is only valid with the TLB.
Random Register Format
31
EntryLo0, EntryLo1 (CP0 Registers 2 and 3, Select 0)
The pair of EntryLo registers act as the interface between the TLB and the TLBR, TLBWI, and TLBWR
instructions. For a TLB-based MMU, EntryLo0 holds the entries for even pages and EntryLo1 holds the
entries for odd pages. The contents of the EntryLo0 and EntryLo1 registers are undefined after an address
error, TLB invalid, TLB modified, or TLB refill exceptions. These registers are only valid with the TLB.
Fields
Description
Read/
Write
Reset
State
Name
Bit(s)
P
31
Probe Failure. Set to 1 when the previous TLBProbe
(TLBP) instruction failed to find a match in the TLB.
R
Undefined
0
30:4
Must be written as zero; returns zero on read.
0
0
Index
3:0
Index to the TLB entry affected by the TLBRead and
TLBWrite instructions.
R/W
Undefined
Table 2.27 Index Register Field Descriptions
4 3
0
0
Random
Fields
Description
Read/
Write
Reset
State
Name
Bit(s)
0
31:4
Must be written as zero; returns zero on read.
0
0
Random
3:0
TLB Random Index
R
TLB
Entries - 1
Table 2.28 Random Register Field Descriptions