IDT Ethernet Interfaces
Ethernet Clock Prescalar
79RC32438 User Reference Manual
11 - 34
November 4, 2002
Notes
Ethernet Clock Prescalar
The Ethernet interfaces share an 8-bit clock prescalar which is used to generate the Ethernet manage-
ment clock for shared MII management interface. The ethernet management clock is the media indepen-
dent interface management data clock on the MIIMDC pin. The Ethernet management clock is equal to the
IPBus clock (ICLK) frequency divided by the clock prescalar divisor (DIV) field in the Ethernet management
clock prescalar register (ETHMCP).
Figure 11.35 Ethernet Management Clock Prescalar Register (ETHMCP)
Programming Example
Disclaimer:
Code examples provided by IDT are for illustrative purposes only and should not be relied
upon for developing applications. IDT does not assume liability for any loss or damage that may result from
the use of this code.
*/
#define ETHIPGT_HALF_DUPLEX 0x12
#define ETHIPGT_FULL_DUPLEX 0x15
int reginit( void ) ;
int io_fifo( void ) ;
int addr_rec( void ) ;
int cpu_infc( void ) ;
int eth_mac( void ) ;
int eth_prescale( void ) ;
NV
Description:
Read Data Not Valid.
When this bit is set to 1, a MII management read operation has not com-
pleted and the value in the MII management read data (MIIMRDD) register is not valid.
Initial Value:
0x0
Read Value:
Status
Write Effect:
Read-only
DIV
Description:
Clock Prescalar Divisor.
When the DIV field equals zero, one, two, or three, the internally gen-
erated ethernet management clock is equal to the system clock divided by four. For all other
even values of the DIV field up to 255, the Ethernet management clock is equal to the system
clock divided by the DIV field. Bit zero of the DIV field is always assumed to be zero.
Initial Value:
0x0
Read Value:
Previous value written
Write Effect:
Modify value
ETHMCP
0
31
DIV
0
24
8