IDT Table of Contents
79RC32438 User Reference Manual
iv
November 4, 2002
Notes
Device Read Transaction...........................................................................................................6-11
Burst Device Read Transaction.................................................................................................6-14
Device Write Transaction...........................................................................................................6-15
Burst Device Write Transaction .................................................................................................6-17
Decoupled CPU Device Transactions........................................................................................6-18
Device Decoupled Access Control and Status Register..................................................6-19
Device Decoupled Access Address Register...................................................................6-20
Device Decoupled Access Data Register.........................................................................6-20
7 DDR Controller
Introduction..................................................................................................................................7-1
Features.......................................................................................................................................7-1
Additional Resources...................................................................................................................7-1
DDR Controller Register Description...........................................................................................7-1
Theory of Operation.....................................................................................................................7-1
DDR Address Multiplexing Scheme...................................................................................7-3
DDR Command Encoding..................................................................................................7-5
DDR Registers.............................................................................................................................7-5
DDR Control Register ........................................................................................................7-5
DDR Read Data Capture Register.....................................................................................7-9
DDR Address Mapping ....................................................................................................7-11
DDR [0|1] Base Register..................................................................................................7-12
DDR [0|1] Mask Register..................................................................................................7-13
DDR 0 Alternate Base Register .......................................................................................7-13
DDR 0 Alternate Mask Register.......................................................................................7-14
DDR 0 Alternate Mapping Register..................................................................................7-14
DDR Data Bus Multiplexing..............................................................................................7-14
DDR Initialization.......................................................................................................................7-16
DDR Custom Transaction Register..................................................................................7-17
DDR Refresh Timer...................................................................................................................7-18
Refresh Timer Count Register..........................................................................................7-18
Refresh Timer Compare Register ....................................................................................7-19
Refresh Timer Control Register........................................................................................7-19
DDR Read Transaction..............................................................................................................7-20
DDR Write Transaction..............................................................................................................7-21
DDR Refresh Transaction..........................................................................................................7-23
DDR Custom Transaction..........................................................................................................7-24
Example of DDR SDRAM Initialization......................................................................................7-25
8 Interrupt Controller
Introduction..................................................................................................................................8-1
Features.......................................................................................................................................8-1
Block Diagram .............................................................................................................................8-2
Interrupt Controller Register Description .....................................................................................8-2
Interrupt Pending [2..6] Register........................................................................................8-3
Interrupt Test [2..6] Register...............................................................................................8-3
Interrupt Mask [2..6] Register.............................................................................................8-4