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IDT EJTAG System
Functional Description
79RC32438 User Reference Manual
20 - 4
November 4, 2002
Notes
Data Hardware Breakpoint Register
Table 20.4 summarizes the data hardware breakpoints, which are controlled through a number of
memory-mapped registers. Certain registers are provided for each implemented data hardware breakpoint,
as indicated with an “n”. General information about the data hardware breakpoint registers is found in
section “Data Breakpoint Registers” on page 20-47.
Register
Name
Register
Mnemonic
Functional Description
Reference
Instruction
Breakpoint
Status
IBS
Indicates number of instruction hard-
ware breakpoints and status on a previ-
ous match.
See section “Instruction
Breakpoint Status (IBS)
Register” on page 20-43.
Instruction
Breakpoint
Address n
IBAn
Address to compare for breakpoint n.
See section “Instruction
Breakpoint Address n (IBAn)
Register” on page 20-44.
Instruction
Breakpoint
Address Mask n
IBMn
Mask for address comparison for
breakpoint n.
See section “Instruction
Breakpoint Address Mask n
(IBMn) Register” on page
20-45.
Instruction
Breakpoint ASID
n
IBASIDn
ASID value to compare for breakpoint
n.
See section “Instruction
Breakpoint ASID n
(IBASIDn) Register” on
page 20-45.
Instruction
Breakpoint Con-
trol n
IBCn
Control of breakpoint n comparison of
ASID and generated event on match.
See section “Instruction
Breakpoint Control n (IBCn)
Register” on page 20-46.
Table 20.3 Overview of Instruction Hardware Breakpoint Registers
Register
Name
Register
Mnemonic
Functional Description
Reference
Data Breakpoint
Status
DBS
Indicates number of data hardware
breakpoints and status on a previous
match.
See section “Data Break-
point Status (DBS) Register”
on page 20-47.
Data Breakpoint
Address n
DBAn
Address to compare for breakpoint n.
See section “Data Break-
point Address n (DBAn)
Register” on page 20-48.
Data Breakpoint
Address Mask n
DBMn
Mask for address comparison for
breakpoint n.
See section “Data Break-
point Address Mask n
(DBMn) Register” on page
20-49.
Table 20.4 Overview of Data Hardware Breakpoint Registers (Part 1 of 2)