參數(shù)資料
型號(hào): 28F3204C3
廠商: Intel Corp.
英文描述: 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級(jí)堆芯片封裝存儲(chǔ)器)
中文描述: 3伏高級(jí)堆疊芯片級(jí)封裝存儲(chǔ)器(3V的高級(jí)堆芯片封裝存儲(chǔ)器)
文件頁數(shù): 9/62頁
文件大?。?/td> 538K
代理商: 28F3204C3
E
28F1602C3, 28F3204C3
9
PRODUCT PREVIEW
1,048,576 x16 bit (16 Mbit)
2,097,152 x16 bit (32 Mbit)
3 Volt Advanced+ Boot Block
Flash Memory
131,072 x16 bit (2 Mbit)
262,144 x16 bit (4 Mbit)
SRAM
F-CE#
F-OE#
F-WE#
F-RP#
F-WP#
A
17-19
/A
18-20
A
0-16
/A
0-17
S-CS
1
#
S-CS
2
S-OE#
S-WE#
S-UB#
S-LB#
DQ
0-15
S-V
CC
S-GND
F-V
PP
F-V
CC
F-GND
Figure 2. 3 Volt Advanced+ Stacked Chip Scale Package Block Diagram
4.1
Bus Operation
The 3 Volt Advanced+ Stacked-CSP memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the Stacked-CSP conform to standard
microcontroller bus cycles. Four control balls dictate
the data flow in and out of the flash component:
F-CE#, F-OE#, F-WE# and F-RP#. Four control
balls handle the data flow in and out of the SRAM
component: S-CS
1
#, S-CS
2
, S-OE#, and S-WE#
These bus operations are summarized in Tables 2
and 3.
4.1.1
READ
The SRAM has one read mode while the flash
memory has four read modes: read array, read
configuration, read status and read query. These
flash
memory
read
modes
are
accessible
independent of the F-V
voltage. The appropriate
read mode command must be issued to the flash
memory to enter the corresponding mode. Upon
initial device power-up or after exit from reset, the
flash device automatically defaults to read array
mode.
F-CE# and F-OE# must be driven active to obtain
data from the flash component. at the outputs.
S-CS
1
#, S-CS
2
, and S-OE# must be driven active
to obtain data from the SRAM device. For all reads
operations, F-WE#, S-WE# and F-RP# must be at
V
IH
. Figure 6 illustrates a flash read cycle.
4.1.2
OUTPUT DISABLE
With F-OE# and S-OE# inactive, the Stacked-CSP
outputs are disabled. Output balls are placed in a
high-mpedance state.
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