參數(shù)資料
型號(hào): 28F3204C3
廠商: Intel Corp.
英文描述: 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級(jí)堆芯片封裝存儲(chǔ)器)
中文描述: 3伏高級(jí)堆疊芯片級(jí)封裝存儲(chǔ)器(3V的高級(jí)堆芯片封裝存儲(chǔ)器)
文件頁數(shù): 40/62頁
文件大小: 538K
代理商: 28F3204C3
28F1602C3, 28F3204C3
E
40
PRODUCT PREVIEW
11.4.2
SIMULTANEOUS BUS OPERATIONS
Operations that require both the SRAM and Flash
to be in active mode are disallowed. An example of
these cases would include simultaneous reads on
both the flash and SRAM, which would result in
contention for the data bus, and thus would not
produce the intended result. Finally, a read of one
device a write of the other similar to the conditions
of direct memory access (DMA) operation are also
not within the recommended operating conditions.
11.5
Printed Circuit Board Notes
The Intel Stacked CSP will save significant space
on your PCB by combining two chips into one BGA
style
package.
Intel
0.8 mm pitch that can be routed on your Printed
Circuit Board with conventional design rules. Trace
widths of 0.127 mm (0.005 inches) are typical.
Unused balls in the center of the package are not
populated to further increase the routing options.
Standard surface mount process and equipment
can be used for the Intel Stacked CSP.
Stacked
CSP
has
a
Land Pad Diameter: 0.35 mm (0.0138 in)
Solder Mask Opening: 0.50 mm (0.0198 in)
Trace Width: 0.127 mm (0.005 in)
Trace Spaces: 0.160 mm (0.00625 in)
Via Capture Pad: 0.51 mm (0.020 in)
Via Drill Size: 0.25 mm (0.010 in)
NOTE:
Top View
Figure 14. Standard PCB Design Rules Can be
Used with Stacked CSP Devices
11.6
System Design Notes Summary
The new Advanced+ Boot Block Stacked CSP
allows higher levels of memory component
integration. Different power supply configurations
can be used within the system to achieve different
objectives. At least three 0.1
μ
f capacitors should
be used to decouple the devices within a system.
SRAM reads or writes during a flash program or
erase are supported operations. Standard printed
circuit board technology can be used.
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