參數(shù)資料
型號: 28F3204C3
廠商: Intel Corp.
英文描述: 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級堆芯片封裝存儲(chǔ)器)
中文描述: 3伏高級堆疊芯片級封裝存儲(chǔ)器(3V的高級堆芯片封裝存儲(chǔ)器)
文件頁數(shù): 39/62頁
文件大小: 538K
代理商: 28F3204C3
E
28F1602C3, 28F3204C3
39
PRODUCT PREVIEW
S-V
SSQ
D10
SRAM DIE
FLASH DIE
SUBSTRATE
XX
S-X
F-X
Substrate connection to package ball
SRAM die bond pad connection
Flash die bond pad connection
S-V
CCQ
S-V
CC
S-V
SS
F-V
PP
F-V
SSQ
F-V
CC
F-V
CCQ
F-V
SS
H8
A9
D9
E4
D3
NOTES:
1.
2.
Substrate connections refer to ballout locations shown in Figure 1.
0.1
μ
f capacitors should be used with D9, D10 and E4.
Figure 13. Typical Flash+SRAM Substrate Power and Ground Connections
Figure 13 shows that the flash V
CC
and V
CCQ
lines
are tied together within the substrate; the diagram
also shows that the SRAM V
CC
and V
CCQ
lines are
ties together within the substrate of the package.
Because of this, it is highly recommended that
systems use a 0.1
μ
f capacitor for each of the D9,
D10, and E4 grid ballout locations (see Figure 1 for
ballout). These capacitors are necessary to avoid
undesired conditions created by excess noise.
11.4
Simultaneous Operation
The term simultaneous operation in used to
describe the ability to read or write to the SRAM
while also programming or erasing flash. In
addition, F-CE#, S-CS
# and S-CS should not be
enabled at the same time. Simultaneous operation
of the can be summarized by the following:
Flash Program or Erase Operations during and
SRAM read/write are allowed
Simultaneous Bus Operations between the
Flash and SRAM are
not
allowed (bus
contention)
11.4.1
SRAM OPERATION DURING FLASH
“BUSY”
This functionality provides the ability to use both the
flash and the SRAM
“at the same time” within a
system, similar to the operation of two devices with
separate footprints. This operation can be achieved
by following the appropriate timing constraints
within a system.
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