參數(shù)資料
型號(hào)： 28F3204C3
廠商： Intel Corp.
英文描述： 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級(jí)堆芯片封裝存儲(chǔ)器)
中文描述： 3伏高級(jí)堆疊芯片級(jí)封裝存儲(chǔ)器（3V的高級(jí)堆芯片封裝存儲(chǔ)器）
文件頁數(shù)： 13/62頁
文件大?。?/td> 538K
代理商： 28F3204C3
E
being changed to a
“0.” If the user attempts to
program “1”s, the memory cell contents do not
change and no error occurs.
28F1602C3, 28F3204C3
13
PRODUCT PREVIEW
The status register indicates programming status:
while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling
either F-CE# or F-OE#. While programming, the
only valid commands are Read Status Register,
Program Suspend, and Program Resume.
When programming is complete, the program status
bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status
register is set to indicate a program failure. If SR.3
is set then F-V
PP
was not within acceptable limits,
and the WSM did not execute the program
command. If SR.1 is set, a program operation was
attempted on a locked block and the operation was
aborted.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, to prevent inadvertent status register
reads, be sure to reset the CUI to read array mode.
5.5.1
SUSPENDING AND RESUMING
PROGRAM
The Program Suspend command halts an in
-
progress program operation so that data can be
read from other locations of memory. Once the
programming process starts, writing the Program
Suspend command to the CUI requests that the
WSM
suspend
the
program
predetermined points in the program algorithm).
The device continues to output status register data
after the Program Suspend command is written.
Polling status register bits SR.7 and SR.2 will
determine when the program operation has been
suspended (both will be set to “1”). t
WHRH1
/t
EHRH1
specify the program suspend latency.
sequence
(at
A Read Array command can now be written to the
CUI to read data from blocks other than that which
is suspended. The only other valid commands,
while program is suspended, are Read Status
Register, Read Configuration, Read Query, and
Program Resume. After the Program Resume
command is written to the flash memory, the WSM
will continue with the programming process and
status register bits SR.2 and SR.7 will automatically
be cleared. The device automatically outputs status
register data when read (see Figure 16 in Appendix
A,
Program Suspend/Resume Flowchart
) after the
Program Resume command is written. F-V
PP
must
remain at the same F-V
PP
level used for program
while in program suspend mode. F-RP# must also
remain at V
IH
.
5.6
Erase Mode
To erase a block, write the Erase Set
-
up and Erase
Confirm commands to the CUI, along with an
address identifying the block to be erased. This
address is latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits within the block being set to “1.” Only one
block can be erased at a time. The WSM will
execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits
within the block to “1,” then verify that all bits within
the block are sufficiently erased. While the erase
executes, status bit 7 is a “0.”
When the status register indicates that erasure is
complete, check the erase status bit to verify that
the erase operation was successful. If the Erase
operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase
failure. If F-V
was not within acceptable limits
after the Erase Confirm command was issued, the
WSM will not execute the erase sequence; instead,
SR.5 of the status register is set to indicate an
erase error, and SR.3 is set to a “1” to identify that
F-V
PP
supply voltage was not within acceptable
limits.
After an erase operation, clear the status register
(50H) before attempting the next operation. Any
CUI instruction can follow after erasure is
completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in
read array mode after the erase is complete.
5.6.1
SUSPENDING AND RESUMING
ERASE
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase
-
sequence interruption in
order to read data from or program data to another
block in memory. Once the erase sequence is
started, writing the Erase Suspend command to the
CUI
suspends
the
erase
predetermined point in the erase algorithm. The
status register will indicate if/when the erase
operation has been suspended. Erase suspend
latency is specified by t
WHRH2
/t
EHRH2
.
sequence
at
a
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