參數(shù)資料
型號： 28F3204C3
廠商： Intel Corp.
英文描述： 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級堆芯片封裝存儲器)
中文描述： 3伏高級堆疊芯片級封裝存儲器（3V的高級堆芯片封裝存儲器）
文件頁數(shù)： 7/62頁
文件大?。?/td> 538K
代理商： 28F3204C3
E
28F1602C3, 28F3204C3
7
PRODUCT PREVIEW
Table 1. 3 Volt Advanced+ Stacked-CSP Ball Descriptions
Symbol
Type
Name and Function
A
0
–A
20
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally latched
during a program or erase cycle.
Flash: 16-Mbit x 16, A[0-19]; 32-Mbit x 16, A[0-20]
SRAM: 2-Mbit x 16, A[0-16]; 4-Mbit x 16, A[0-17]
DATA INPUTS/OUTPUTS:
Inputs array data for SRAM write operations and on
the second F-CE# and F-WE# cycle during a flash Program command. Inputs
commands to the flash’s Command User Interface when F-CE# and F-WE# are
active. Data is internally latched. Outputs array, configuration and status register
data. The data balls float to tri-state when the chip is de-selected or the outputs
are disabled.
DQ
0
–
DQ
15
INPUT /
OUTPUT
F-CE#
INPUT
FLASH CHIP ENABLE:
Activates the flash internal control logic, input buffers,
decoders and sense amplifiers. F-CE# is active low. F-CE# high de-selects the
flash memory device and reduces power consumption to standby levels.
S-CS
1
#
INPUT
SRAM CHIP SELECT1:
Activates the SRAM internal control logic, input buffers,
decoders and sense amplifiers. S-CS
1
# is active low. S-CS
1
# high de-selects the
SRAM memory device and reduces power consumption to standby levels.
S-CS
2
INPUT
SRAM CHIP SELECT2:
Activates the SRAM internal control logic, input buffers,
decoders and sense amplifiers. S-CS
2
is active high. S-CS
2
low de-selects the
SRAM memory device and reduces power consumption to standby levels.
F-OE#
INPUT
FLASH OUTPUT ENABLE:
Enables flash’s outputs through the data buffers
during a read operation. F-OE# is active low.
S-OE#
INPUT
SRAM OUTPUT ENABLE:
Enables SRAM’s outputs through the data buffers
during a read operation. S-OE# is active low.
F-WE#
INPUT
FLASH WRITE ENABLE:
Controls writes to flash’s command register and
memory array. F-WE# is active low. Addresses and data are latched on the rising
edge of the second F-WE# pulse.
S-WE#
INPUT
SRAM WRITE ENABLE:
Controls writes to the SRAM memory array. S-WE# is
active low.
S-UB#
INPUT
SRAM UPPER BYTE ENABLE:
Enable the upper bytes for SRAM (DQ
8
–DQ
15
).
S-UB# is active low.
S-LB#
INPUT
SRAM LOWER BYTE ENABLE:
Enable the lower bytes for SRAM (DQ
0
–DQ
7
).
S-LB# is active low.
F-RP#
INPUT
FLASH RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to
control reset/deep power-down mode.
When F-RP# is at logic low, the device is in reset/deep power-down mode
,
which drives the outputs to High-Z, resets the Write State Machine, and
minimizes current levels (I
CCD
).
When F-RP# is at logic high, the device is in standard operation
. When
F-RP# transitions from logic-low to logic-high, the device resets all blocks to
locked and defaults to the read array mode.
相關(guān)PDF資料
PDF描述
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