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參數(shù)資料
| 型號(hào)： | 28F3204C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級(jí)堆芯片封裝存儲(chǔ)器) |
| 中文描述： | 3伏高級(jí)堆疊芯片級(jí)封裝存儲(chǔ)器（3V的高級(jí)堆芯片封裝存儲(chǔ)器） |
| 文件頁數(shù)： | 23/62頁 |
| 文件大?。?/td> | 538K |
| 代理商： | 28F3204C3 |
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E
9.4
28F1602C3, 28F3204C3
23
PRODUCT PREVIEW
DC Characteristics
(continued)
2.7 V
–3.3 V
Sym
Parameter
Device
Note
Min
Max
Unit
Test Conditions
V
IL
Input Low Voltage
Flash/
SRAM
–0.4
V
CC
*0.22
V
CC
+0.3
V
V
IH
Input High Voltage
Flash/
SRAM
2.2
V
V
OL
Output Low Voltage
Flash/
SRAM
7
–0.10
0.10
V
F-V
CC
/S-V
CC
= V
CC1
Min
I
OL
= 100
μ
A
F-V
CC
/S-V
CC
= V
CC1
Min
I
OH
= –100
μ
A
V
OH
Output High Voltage
Flash/
SRAM
7
V
CC
–
0.1
V
V
PPLK
F-V
Lock-Out
Voltage
Flash
3
1.0
V
Complete Write Protection
V
PP1
F-V
during
Program / Erase
Operations
Flash
3
1.65
3.3
V
V
PP2
3,6
11.4
12.6
V
LKO
V
Prog/Erase Lock
Voltage
Flash
1.5
V
NOTES:
1.
2.
All currents are in RMS unless otherwise noted. Typical values at nominal F-V
CC
/S-V
CC
, T
A
=
+25 °C.
I
CCES
and I
CCWS
are specified with device de-selected. If device is read while in erase suspend, current draw is sum of
I
CCES
and I
CCR
. If the device is read while in program suspend, current draw is the sum of I
CCWS
and I
CCR
.
Erase and Program are inhibited when F-V
PP
< V
PPLK
and not guaranteed outside the valid F-V
PP
ranges of V
PP1
and V
PP2
.
Sampled, not 100% tested.
Automatic Power Savings (APS) reduces I
CCR
to approximately standby levels in static operation (CMOS inputs).
Applying F-V
= 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. F-V
PP
may be connected to 12 V for a total of 80 hours maximum. See Section
8.1 for details.
The test conditions F-V
CC
/S-V
CC
= V
CC1
Min refer to the maximum or minimum V
CC1
or V
CC2
voltage listed at the top of
each column.
3.
4.
5.
6.
7.
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