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參數(shù)資料
| 型號： | 28F3204C3 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級堆芯片封裝存儲器) |
| 中文描述： | 3伏高級堆疊芯片級封裝存儲器（3V的高級堆芯片封裝存儲器） |
| 文件頁數(shù)： | 15/62頁 |
| 文件大?。?/td> | 538K |
| 代理商： | 28F3204C3 |
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E
28F1602C3, 28F3204C3
15
PRODUCT PREVIEW
Table 6. Flash Memory Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready
(WSMS)
0 = Busy
Check Write State Machine bit first to determine
Word Program or Block Erase completion, before
checking Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.”
ESS bit remains set to “1” until an Erase Resume
command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the
max. number of erase pulses and is still unable to
verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1,” WSM has attempted but
failed to program a word/byte.
SR.3 = F-V
PP
STATUS (VPPS)
1 = F-V
PP
Low Detect, Operation Abort
0 = F-V
PP
OK
The F-V
PP
status bit does not provide continuous
indication of V
PP
level. The WSM interrogates F-V
PP
level only after the Program or Erase command
sequences have been entered, and informs the
system if F-V
PP
has not been switched on. The
F-V
PP
is also checked before the operation is verified
by the WSM. The F-V
PP
status bit is not guaranteed
to report accurate feedback between V
PPLK
and V
PP1
min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts
execution and sets both WSMS and PSS bits to “1.”
PSS bit remains set to “1” until a Program Resume
command is issued.
SR.1 = BLOCK LOCK STATUS
1 = Prog/Erase attempted on a locked
block; Operation aborted.
0 = No operation to locked blocks
If a program or erase operation is attempted to one
of the locked blocks, this bit is set by the WSM. The
operation specified is aborted and the device is
returned to read status mode.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
This bit is reserved for future use and should be
masked out when polling the status register.
NOTE:
1.
A Command Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set.
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