參數(shù)資料
型號(hào)： 28F3204C3
廠商： Intel Corp.
英文描述： 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級(jí)堆芯片封裝存儲(chǔ)器)
中文描述： 3伏高級(jí)堆疊芯片級(jí)封裝存儲(chǔ)器（3V的高級(jí)堆芯片封裝存儲(chǔ)器）
文件頁(yè)數(shù)： 37/62頁(yè)
文件大?。?/td> 538K
代理商： 28F3204C3
E
11.1.1
28F1602C3, 28F3204C3
37
PRODUCT PREVIEW
FLASH + SRAM FOOTPRINT
INTEGRATION
The Stacked Chip Scale Package memory solution
can be used to replace a subset of the memory
subsystem within a design. Where a previous
design may have used two separate footprints for
SRAM and Flash, you can now replace with the
industry standard I-ballout of the Stacked CSP
device. This allows for an overall reduction in board
space, which allows the design to integrate both the
flash and the SRAM into one component.
11.1.2
ADVANCED+ BOOT BLOCK FLASH
MEMORY FEATURES
Advanced+ Boot Block adds the following new
features
to
Intel
Advanced
architecture:
Boot
Block
Instant, individual block locking provides
software/hardware
controlled,
locking/unlocking of any block with zero latency
to protect code and data.
A 128-bit Protection Register enables system
security implementations.
Improved
12 V
production
simplifies the system configuration required to
implement 12 V fast programming
Common
Flash
Interface
component information on the chip to allow
software-independent device upgrades
For more information on specific advantages of the
Advanced+ Boot Block Flash Memory, please see
AP-658 Designing with the Advanced+ Boot Block
Flash Memory Architecture.
independent
programming
(CFI)
provides
11.2
Flash Control Considerations
The flash device is protected against accidental
block erasure or programming during power
transitions. Power supply sequencing is not
required, since
the device is indifferent as to which
power supply, F-V
PP
or F-V
CC
, powers-up first.
Example Flash power supply configurations are
shown in Figure 12.
11.2.1
F-RP# CONNECTED TO SYSTEM
RESET
The use of F-RP# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
F-RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
System designers must guard against spurious
writes when F-V
CC
voltages are above V
LKO
. Since
both F-WE# and F-CE# must be low for a command
write, driving either signal to V
IH
will
inhibit writes to
the device. The CUI architecture provides additional
protection since alteration of memory contents can
only occur after successful completion of the two-
step command sequences. The device is also
disabled until F-RP# is brought to V
IH
, regardless of
the state of its control inputs.
By holding the device in reset (F-RP# connected to
system PowerGood) during power-up/down, invalid
bus conditions during power-up can be masked,
providing yet another level of memory protection.
11.2.2
F-V
CC
, F-V
PP
AND F-RP# TRANSITION
The CUI latches commands as issued by
system
software and is not altered by F-V
PP
or F-CE#
transitions or WSM actions. Its default state upon
power-up, after exit from reset mode or after F-V
CC
transitions above V
LKO
(Lockout voltage), is read
array mode.
After any program or block erase operation is
complete (even after F-V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
相關(guān)PDF資料
PDF描述
28F1604C3 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲(chǔ)器和靜態(tài)存儲(chǔ)器)
28F160C18 1.8V Advanced+ Boot Block Flash Memory(1.8V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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