參數(shù)資料
型號(hào)： Z87200
廠商： ZILOG INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 9/54頁(yè)
文件大?。?/td> 449K
代理商： Z87200
Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-9
4
A.C. CHARACTERISTICS - TRANSMITTER
Operating Conditions: V
DD
= 5.0V
±
5%, V
SS
= 0V
T
A
0
°
C to +70
°
C
Min
Symbol
f
TXIFCLK
Parameter
Max
45.056
20.0
Units
MHz
MHz
Conditions
TXIFCLK Frequency
Z0200045FSC
Z0200020FSC or if
TXIFOUT is used
t
CH
t
CL
t
SU
t
HD
t
CT
TXIFCLK Pulse width, High
TXIFCLK Pulse width, Low
TXIN to TXIFCLK setup
TXIN to TXIFCLK hold
TXIFCLK to TXBITPLS,
TXTRKPLS, XACQPLS,
TXIOUT or TXQOUT delay
10
10
3
5
ns
ns
ns
ns
ns
35
Notes:
1. The number of TXIFCLK cycles per cycle of TXCHPPLS is determined by the data stored in bits 5-0 of address 41
H
. It is shown
as 2 in Figure 8 but can be set from 2 to 64.
2. The width of the TXBITPLS, TXTRKPLS and TXACQPLS signal pulses is equal to the period of TXCHPPLS; that is, equal to
the PN chip period.
3. In QPSK mode, the TXBITPLS signal pulses high twice during each symbol period, once during the center chip and once
during the last chip. If the number of chips per symbol is even, the number of chip periods between the TXBITPLS pulse at
the end of the previous symbol and the one in the center of the symbol will be one more than the number of chip periods
between the TXBITPLS pulse in the center of the symbol and the one at the end. The falling edge of the second pulse corre-
sponds to the end of the symbol period.
4. The TXTRKPLS signal pulses high once each symbol period, during the last chip period of that symbol. The falling edge cor-
responds to the end of the symbol period.
5. The TXACQPLS signal pulses high once each burst, transmission, during the last chip of the Acquisition/Preamble symbol.
The falling edge corresponds to the end of this symbol period.
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