參數(shù)資料
型號(hào)： Z87200
廠商： ZILOG INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 32/54頁(yè)
文件大?。?/td> 449K
代理商： Z87200
Z87200
Spread-Spectrum Transceiver
Zilog
4-32
DS96WRL0400
CONTROL REGISTERS
(Continued)
tion Processor will insert a detect pulse at the appropriate
time if a successful correlation is not detected as expected
a priori
Address 2D
H
:
Bits 5-0 — Rx Chips per Data Symbol
The number of PN chips per data symbol in the receiver is
controlled by address 2D
H
. The unsigned value must
range from 1 to 63 (01
H
to 3F
H
), where the number of chips
per data symbol will be this value plus 1. The a priorinum-
ber of PN chips per data symbol, where this value must be
equal to the number of non-zero coefficients stored in the
Data Symbol Coefficient Registers (addresses 17
H
to 26
H
)
for the PN Matched Filter, is used to help control symbol
timing in the receiver. Since acquisition is purely based on
correlation of a single received Acquisition/Preamble sym-
bol, the corresponding number of chips per Acquisi-
tion/Preamble symbol is not required and no similar regis-
ter is provided for such use.
Address 2E
H
:
Receiver Data Symbols per Burst (bits 7-0)
The data stored as two bytes in addresses 2E
H
(LS Byte)
and 3A
H
(MS Byte) define the number of data symbols per
burst. This unsigned value must range from 3 to 65,535
(0003
H
to FFFF
H
), and the number of data symbols per
burst will be this value minus 2, giving a range of 1 to
65,533. Note that the range is slightly different from that
supported by the Z87200’s transmitter. Once the number
of received data symbols processed exceeds this number,
the burst is assumed to have ended and the receiver im-
mediately returns to acquisition mode, ready for the next
burst.
Address 2F
H
:
Missed Detects per Burst Threshold
To monitor the reception quality of the received burst data
symbols, the Z87200 incorporates a feature within its
tracking algorithm that tallies the number of received data
symbols whose PN Matched Filter correlation output did
not exceed the Data Symbol Threshold value.
Whenever a “missed detect” occurs, the tracking algorithm
will generate and insert a detect signal at the sample clock
cycle corresponding to the expected correlation peak in or-
der to maintain a continuous train of data symbols and
symbol clocks. Simultaneously, a “missed detect” pulse
will be generated internally and tallied for the current burst.
When the accumulated number of missed detects is great-
er than the value stored in address 2F
H
, the device will ter-
minate reception of the current burst and return to acquisi-
tion mode to await the next burst.
The unsigned value in address 2F
H
must range from 1 to
255 (01
H
to FF
H
), where this value is the maximum num-
ber of missed detects per burst allowed before the burst
terminates. This function can be disabled by setting bit 5 of
address 30
H
high.
Address 30
H
:
Bit 0 — Manual Detect Enable
While the receiver is in acquisition mode, valid bursts may
be ignored by setting this bit high. When it is set low (nor-
mal operation), the detection of a burst’s Acquisition/Pre-
amble symbol is enabled. Setting this bit high allows the
user to force the device to ignore Acquisition/Preamble
symbols that would normally be successfully acquired.
This feature could be used, for example, in a system em-
ploying multiple receivers with identical PN codes in a
Time Division Multiple Access scheme where time-syn-
chronized device management could be supported
through dynamic setting of this bit.
Acquisition and Tracking Processor
Registers
Bit 1 — Manual Punctual
This bit enables the user to completely disable the internal
tracking circuitry and force symbol information to be trans-
ferred to the demodulator punctually at the symbol rate de-
termined by the number of chips per data symbol informa-
tion programmed into address 2D
H
. This function
overrides the symbol tracking algorithm, although the ab-
sence of a successful correlation will continue to be tallied
as a missed detect and compared against the value stored
in address 2F
H
to monitor signal quality unless disabled by
bit 5 of address 30
H
. When bit 1 is set low, the Z87200 will
operate in its normal mode with symbol timing derived from
the symbol tracking processor; when set high, symbol tim-
ing is derived from the a priorinumber of chips per data
symbol stored in bits 5-0 of address 2D
H
.
Bit 2 — Force Continuous Acquisition
This bit enables the user to force the receiver to remain in
acquisition mode even after successful detection of the
Acquisition/Preamble symbol. When so commanded, the
receiver will continuously process only Acquisition/Pream-
ble symbols and will not switch from acquisition mode. This
function may be used under manual control to receive a
series of repeated Acquisition/Preamble symbols in order
to increase the confidence level of burst detection before
beginning demodulation of the data symbol information.
When this bit is set high, the device will be locked in acqui-
sition mode and the Symbol Tracking Processor will not in-
Table 13. Data Symbol Threshold Storage
ADDR 2C
H
Bits 1-0
Data Thresh. Bits 9-8
ADDR 2B
H
Bits 7-0
Data Thresh. Bid 7-0
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