參數(shù)資料
型號(hào)： Z87200
廠商： ZILOG INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 25/54頁(yè)
文件大小： 449K
代理商： Z87200
Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-25
4
OUTPUT SIGNALS
TXIOUT (Pin 77)
Transmitter In-Phase Output.
TXIOUT is the in-phase
output transmission signal that has been differentially en-
coded and PN spread. TXIOUT changes on the rising
edge of TXIFCLK following the falling edge of TXCHPPLS.
TXQOUT (Pin 76)
Transmitter Quadrature-Phase Output.
TXQOUT is the
quadrature-phase output transmission signal that has
been differentially encoded and PN spread. TXQOUT
changes on the rising edge of TXIFCLK following the fall-
ing edge of TXCHPPLS.
TXIFOUT
7-0
(Pins 66-73)
Transmitter I.F. Output.
TXIFOUT
7-0
is the modulated
transmit output signal from the on-chip BPSK/QPSK mod-
ulator. The signal is composed of the sum of the modulat-
ed TXIOUT and TXQOUT signals, modulated by the NCO
cosine and sine outputs, respectively. Since the modulator
is driven by the Z87200’s NCO, TXIFOUT
7-0
changes on
the rising edges of RXIFCLK, and operation of the
BPSK/QPSK modulator requires that RXIFCLK and TXIF-
CLK be identical and their common frequency not exceed
20 MHz. TXIFOUT
7-0
may be in either two’s complement
or offset binary format according to the setting of bit 1 of
address 40
H
.
TXACQPLS (Pin 60)
Transmitter Acquisition Pulse.
TXACQPLS is an output
signal generated at the final chip of the Acquisition/Pream-
ble symbol. The Acquisition/Preamble symbol is generat-
ed automatically by the Z87200 upon user command (ei-
ther via bit 1 of address 37
H
or MTXEN input) and
immediately precedes transmission of user data. TXACQ-
PLS is then provided to the user to indicate when the final
chip of the Acquisition/Preamble symbol is being transmit-
ted.
TXBITPLS (Pin 63)
Transmitter Bit Pulse.
TXBITPLS is an output signal
used to support transmission timing of user data for either
BPSK or QPSK modes, as programmed by bit 0 of 40
H
.
In BPSK mode, user-provided data is requested by the
Z87200 by a rising edge of TXBITPLS once per symbol.
TXBITPLS requests the data one chip period before the
TXIN data is latched into the device, and TXBITPLS falls
low immediately following the rising edge of TXIFCLK,
where TXIFCLK latches the TXIN value.
In QPSK mode, user-provided data is requested by the
Z87200 by a rising edge of output signal TXBITPLS which
occurs twice per symbol, first one chip period before the
middle of the symbol and then one chip period before the
end of the symbol. TXBITPLS requests the data exactly
one chip cycle period before the TXIN data is latched into
the device. TXBITPLS falls low immediately following the
rising edge of TXIFCLK, where TXIFCLK latches the TXIN
value.
In both BPSK and QPSK modes, the data must be valid on
the second rising edge of TXIFCLK after the rising edge of
TXBITPLS.
TXCHPPLS (Pin 62)
Transmitter Chip Pulse.
TXCHPPLS is an output signal
used to support transmission timing for the device. TXCH-
PPLS pulses high for one TXIFCLK cycle at the PN chip
rate defined by the user. The chip rate is set either by pro-
gramming a value in bits 5-0 of address 41
H
or through use
of the external TXMCHP signal.
TXTRKPLS (Pin 61)
Transmitter Data Track Pulse.
TXTRKPLS is an output
signal that allows monitoring of data symbol transmis-
sions. A rising edge of output signal TXTRKPLS occurs
one chip period before the end of the current data symbol
transmission. TXTRKPLS then falls low immediately fol-
lowing the rising edge of TXIFCLK.
TXACTIVE (Pin 78)
Transmitter Active.
A high level on TXACTIVE indicates
that the transmitter is sending data symbols. This signal
will be set high at the end of the Acquisition/Preamble sym-
bol, indicating the start of the first chip of the first data sym-
bol at the TXIOUT and TXQOUT pins. It will be set low at
the end of the last chip period of the last data symbol of the
burst at the TXIOUT and TXQOUT pins.
RXOUT (Pin 57)
Receiver Output.
RXOUT is the output data of the receiv-
er following downconversion, despreading and demodula-
tion. In BPSK mode, one data bit is provided per symbol;
in QPSK mode, two data bits are provided per symbol with
a half-symbol separation between the bits. Note that, when
the Z87200 is operated in burst mode, the data will be in-
valid during the first symbol of each burst; that is, in BPSK
mode the first bit will be invalid, and in QPSK mode the first
two bits will be invalid.
RXIOUT (Pin 56)
Receiver I Channel Output.
RXIOUT is the I channel out-
put data before dibit-to-serial conversion. RXIOUT can be
used in conjunction with the RXQOUT signal in applica-
tions where the QPSK output data is required as parallel
bit pairs. Note that, when the Z87200 is operated in burst
mode, the first bit of RXIOUT in each burst will be invalid
RXQOUT (Pin 55).
Receiver Q Channel Output.
RXQOUT is the Q channel
output data before dibit-to-serial conversion. RXQOUT
can be used in conjunction with the RXIOUT signal in ap-
plications where the QPSK data is required as parallel bit
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