參數(shù)資料
型號(hào)： Z87200
廠商： ZILOG INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 14/54頁(yè)
文件大?。?/td> 449K
代理商： Z87200
Z87200
Spread-Spectrum Transceiver
Zilog
4-14
DS96WRL0400
FUNCTIONAL BLOCKS
Transmit and Receive Clock Generators
Timing in the transmitter and receiver sections of the
Z87200 is controlled by the Transmit and Receive Clock
Generator Blocks. These blocks are programmable divid-
ers providing signals at the chip and symbol rates (as well
as at multiples and sub-multiples of these frequencies) as
programmed through the Z87200’s control registers. If de-
sired, the complete independence of the transmitter and
receiver sections allows the transmit and receive clocks to
be mutually asynchronous. Additionally, the Z87200 al-
lows external signals to be provided as references for the
transmit (TXMCHP) and receive (RXMSMPL) chip rates.
Given the transmit PN chip rate, the PN-synchronous
transmit symbol rate is then derived from the programmed
number of PN chips per transmit symbol. At the receiver,
symbol synchronization and the receive symbol rate are
determined from processing of the PN matched filter out-
put, or, if desired, can be provided from the programmed
number of PN chips per receive symbol or an external
symbol synch symbol, RXMDET. Burst control is achieved
by means of the transmit and receive Symbols per Burst
counters. These programmable 16-bit counters allow the
Z87200 to operate automatically in burst mode, stopping
at the end of each burst without the need of any external
counters.
Input and Output Processors
When the transmitter and receiver are operating in QPSK
mode, the data to be transmitted and the received data are
processed in pairs of bits (dibits), one bit for the in-phase
(I) channel and one for the quadrature (Q) channel. Dibits
are transmitted and received as single differentially encod-
ed QPSK symbols. Single-bit I/O data is converted to and
from this format by the Input and Output Processors, ac-
cepting TXIN as the serial data to be transmitted and pro-
ducing RXOUT as the serial data output. If desired, the re-
ceived data is also available at the RXIOUT and RXQOUT
pins in (I and Q) dibit format prior to dibit-to-serial conver-
sion. While receive timing is derived by the Z87200 Sym-
bol Tracking Processor, transmit timing is provided by the
Input Processor. In BPSK mode, the Input Processor will
generate the TXBITPLS signal once per symbol to request
each bit of data, while in QPSK mode it will generate the
TXBITPLS signal twice per symbol to request the two bits
of data corresponding to each QPSK symbol.
Differential Encoder
Data to be transmitted is differentially encoded before be-
ing spread by the transmit PN code. Differential encoding
of the signal is fundamental to operation of the Z87200’s
receiver: the Z87200’s DPSK Demodulator computes
“Dot” and “Cross” product functions of the current and pre-
vious symbols’ downconverted I and Q signal components
in order to perform differential decoding as an intrinsic part
of DPSK demodulation.
The differential encoding scheme depends on whether the
modulation format is to be BPSK or QPSK. For DBPSK,
the encoding algorithm is straightforward: output bit(k)
equals input bit(k)
⊕
output bit(k–1), where
⊕
represents
the logical XOR function. For DQPSK, however, the differ-
ential encoding algorithm, as shown in Table 2, is more
complex since there are now sixteen possible new states
depending on the four possible previous output states and
four possible new input states.
Table 2. QPSK Differential Encoder Sequence
New Input
IN(I,Q)
K
0
0
1
1
Previously Encoded OUT(I,Q)
K-1
0
0
1
0
0
1
1
1
1
1
1
0
0
0
0
Newly Encoded OUT (I,Q)K
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
0
1
1
0
1
1
0
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