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參數(shù)資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 21/54頁 |
| 文件大小： | 449K |
| 代理商： | Z87200 |
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Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-21
4
The factor of 1/4 results from truncation of the 2 LSBs of
the signal in the integrator path of the loop so that, when
added to the signal in the direct path, the LSBs of the sig-
nals are aligned. The coefficients K1 and K2 are defined by
the data stored in bits 4-0 of addresses 35
H
and 34
H
, re-
spectively. In addition, bit 5 of addresses 35
H
and 34
H
con-
trol whether the K1 and K2 paths, respectively, are en-
abled. These parameters thus give the user full control of
the Loop Filter characteristics.
RXIIN
7-0
(Pins 91-98)
Receiver In-Phase Input.
RXIIN is an 8-bit input port for
in-phase data from external A/D converters. Data may be
received in either two’s complement or offset binary format
as selected by bit 3 of address 01
H
. The sampling rate of
the RXIIN signals (the I.F. sampling rate of the A/Ds) may
be independent of the baseband sampling rate (the Down-
converter integrate and dump rate) and the PN chip rate,
but must be equal to RXIFCLK and at least two times
greater than the baseband sampling rate. Since the base-
band sampling rate must be set at twice the PN chip rate,
the I.F. sampling rate must thus be at least four times the
PN chip rate. Data on the pins is latched and processed by
RXIFCLK.
RXQIN
7-0
(Pins 2-9)
Receiver Quadrature-Phase Input.
RXQIN is an 8-bit in-
put port for quadrature-phase data from external A/D con-
verters. Data may be received in either two’s complement
or offset binary format as selected by bit 3 of address 01
H
.
As with RXIIN, the sampling rate of the RXQIN signals may
be independent of the baseband sampling and PN chip
rates in the receiver, but must be at least two times greater
than the baseband sample rate (or, equivalently, at least
four times greater than the PN chip rate). Data on the pins
is latched and processed by RXIFCLK.
Figure 9. Frequency Discriminator and Loop Filter Detail
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