參數(shù)資料
型號(hào)： Z87200
廠商： ZILOG INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 22/54頁(yè)
文件大小： 449K
代理商： Z87200
Z87200
Spread-Spectrum Transceiver
Zilog
4-22
DS96WRL0400
FUNCTIONAL BLOCKS
(Continued)
Note that if the Z87200 is to be used in Direct I.F. Sampling
Mode, then the I.F. signal should be input to the RXIIN in-
put port only. RXQIN must then be held to arithmetic zero
according to the chosen ADC format as selected by bit 3
of address 01
H
. In other words, to support Direct I.F. Sam-
pling, RXQIN must be tied to a value of 127 or 128 if offset
binary input format has been selected or to a value of 0 if
two’s complement input format has been selected.
RXMSMPL (Pin 84)
Receiver Manual Sample Clock.
RXMSMPL enables the
user to externally generate (independent of the I.F. sam-
pling clock, RXIFCLK) the baseband sampling clock used
for all processing after the digital downconverter, including
the dump rate of the Integrate and Dump filters. This fea-
ture is useful in cases where a specific baseband sample
rate is required that may not be derived by the internal
sample rate timing generator which generates clock sig-
nals at integer sub-multiples of RXIFCLK. The signal is in-
ternally synchronized to RXIFCLK to avoid intrinsic race or
hazard timing conditions. There must be at least two cy-
cles of RXIFCLK to every cycle of RXMSMPL, and
RXMSMPL should be set to twice the nominal receive PN
chip rate.
When bit 0 of address 01
H
is set high, a rising edge on
RXMSMPL will initiate a baseband sampling clock pulse to
the Integrate and Dump filters and subsequent circuitry
(e.g., PN Matched Filter, DPSK Demodulator, Power Esti-
mator, etc.). The rising edge of RXMSMPL is synchronized
internally so that, on the second rising edge of RXIFCLK
that follows the rising edge of RXMSMPL, a pulse is inter-
nally generated that clocks the circuitry that follows. On the
third rising RXIFCLK edge, the contents of the Integrate
and Dump Filters of the Downconverter are transferred to
the PN Matched Filter. The extra one RXIFCLK delay be-
fore transfer of the contents of the filters enables the inter-
nally generated baseband sampling clock to be free of
race conditions at the interface between the Downconvert-
er and PN Matched Filter.
RXMDET (Pin 88)
Receiver Manual Detect.
RXMDET enables the user to
externally generate symbol timing, bypassing and overrid-
ing the internal symbol power estimation and tracking cir-
cuitry. This function may be useful when the dynamic char-
acteristics of the transmission environment require
unusual adjustments to the symbol timing.
When bit 0 of address 30
H
is set high (Manual Detect En-
able) and when bit 0 of address 31
H
is set low, a rising
edge of RXMDET will generate a symbol correlation detect
pulse. The function can also be performed by means of bit
0 of address 31
H
. The RXMDET input and bit 0 of address
31
H
are logically ORed together so that, when either one
is held low, a rising edge on the other triggers the manual
detect function. The rising edge of RXMDET is synchro-
nized internally so that, on the second rising edge of the
baseband sampling clock that follows the rising edge of
RXMDET, the correlated outputs of the PN Matched Filter
I and Q channels will be transferred to the DPSK demodu-
lator.
RXMABRT (Pin 87)
Receiver Manual Abort.
RXMABRT enables the user to
manually force the Z87200 to cease reception of the cur-
rent burst of data symbols and prepare for acquisition of a
new burst. This function can be used to reset the receiver
and prepare to receive a priority transmission signal under
precise timing control, giving the user the ability to control
the current status of the receiver for reasons of priority, sig-
nal integrity, etc.
When bit 0 of address 32
H
is set low, a rising edge on
RXMABRT will execute the abort function. The function
can also be performed under microprocessor control by
means of bit 0 of address 32
H
. The RXMABRT input and
bit 0 of address 32
H
are logically ORed together so that,
when either one is held low, a rising edge on the other trig-
gers the abort function. The second rising edge of the
baseband sampling clock that follows a rising edge of
RXMABRT will execute the abort and also clear the sym-
bols-per-burst, samples-per-symbol, and missed-detects-
per-burst counters. The counters will be reactivated on the
detection of the next burst preamble or by a manual detect
signal.
RXIFCLK (Pin 12)
Receiver I.F. Clock.
RXIFCLK is the master clock of the
NCO and all the receiver blocks. All clocks in the receiver
section and the NCO, internal or external, are generated or
synchronized internally to the rising edge of RXIFCLK. The
frequency of RXIFCLK must be at least four times the PN
chip rate of the received signal. When bit 0 of address 01
H
is set low, the baseband sampling clock, required to be at
twice the nominal PN chip rate, will be derived from RXIF-
CLK according to the setting of bits 5-0 of address 02
H
.
MNCOEN (Pin 86)
Manual NCO Enable.
MNCOEN allows the power con-
sumed by the operation of the NCO circuitry to be mini-
mized when the Z87200 is not receiving and not transmit-
ting data. The NCO can also be disabled while the Z87200
is transmitting as long as the Z87200’s on-chip
BPSK/QPSK modulator is not being used. With the instan-
taneous acquisition properties of the PN Matched Filter, it
is often desirable to shut down the receiver circuitry to re-
duce power consumption, resuming reception periodically
until an Acquisition/Preamble symbol is acquired. Setting
MNCOEN low holds the NCO in a reset state; setting MN-
COEN high then reactivates the NCO, where it is neces-
sary to then reload the frequency control word into the
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