參數(shù)資料
型號(hào)： Z87200
廠商： ZILOG INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 39/54頁(yè)
文件大?。?/td> 449K
代理商： Z87200
Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-39
4
Bit 1 — Offset Binary Output
The TXIFOUT
7-0
output signals can be in either two’s com-
plement or offset binary formats. Since all internal pro-
cessing in the device uses two’s complement format sig-
nals, the MSB of the two’s complement modulated
transmitter output must be inverted if the output is to be in
offset binary format.
When this bit is set high, the TXIFOUT
7-0
output will be in
offset binary format and, when it is set low, the signal will
be in two’s complement format. In two’s complement for-
mat, the 8-bit output values range from –128 to +127 (80
H
to 7F
H
); in offset binary format, the values range from 0 to
+255 (00
H
to FF
H
).
Bit 2 — Manual Chip Clock Enable
This bit enables the PN chip rate to be controlled by either
the internal chip rate clock generator or by the external in-
put signal TXMCHP. The TXMCHP input allows the user
to manually insert a single PN chip clock pulse or continu-
ous stream of pulses. This feature is useful in cases where
a specific chip rate is required that cannot be derived by
the internal clock generator which generates clocks of in-
teger sub-multiples of the frequency of TXIFCLK. The sig-
nal is internally synchronized to TXIFCLK to avoid race or
hazard timing conditions.
When this bit is set high, TXMCHP will provide the PN chip
rate clock; when it is set low, the clock will be provided by
the internal chip rate clock generator controlled by bits 5-0
of address 41
H
.
Bit 3 — Invert Symbol
This bit allows the user to invert the I and Q channel bits
following differential encoding and before being spread by
the PN code. This function has the same effect as inverting
the PN code, which may be useful in some cases.
When this bit is set high, the encoded I and Q channel bits
will be inverted; when it is set low, the I and Q channel bits
will not be inverted.
Address 41
H
:
Bits 5-0 — TXIFCLK Cycles per Chip
Bits 5-0 set the transmitter baseband PN chip rate to the
frequency of TXIFCLK/(n+1), where n is the value stored
in bits 5-0. The value of the data stored in bits 5-0 must
range from 1 to 63 (01
H
to 3F
H
). This feature is useful
when the PN chip rate required is an integer sub-multiple
of the frequency of TXIFCLK. In cases where a chip rate is
required that is not an integer sub-multiple of the frequency
of TXIFCLK, the rate may be controlled externally using
TXMCHP.
Address 42
H
:
Bits 5-0 — Tx Chips per Data Symbol
The number of chips per data symbol in the transmitter is
stored in bits 5-0 of address 42
H
. The unsigned value must
range from 1 to 63 (01
H
to 3F
H
), and the number of chips
per data symbol will be this value plus 1. This value con-
trols data symbol timing in the transmitter.
Address 43
H
:
Bits 5-0 — Tx Chips per Acquisition/Preamble Symbol
The number of chips per Acquisition/Preamble symbol in
the transmitter is stored in bits 5-0 of address 43
H
. The un-
signed value must range from 1 to 63 (01
H
to 3F
H
), and the
number of chips per data symbol will be this value plus 1.
This value controls the Acquisition/Preamble symbol tim-
ing in the transmitter.
Addresses 44
H
through 4B
H
:
Transmitter Acquisition/Preamble Symbol Code
Each Z87200 burst transmission begins with an Acquisi-
tion/Preamble symbol and is then followed by the actual in-
formation data symbols. Two separate and independent
PN codes can be employed, one for the Acquisition/Pre-
amble symbol, the other for the information symbols. Ac-
cordingly, the Z87200 Transmit PN Code Generators, like
the receiver’s PN Matched Filter, support independent PN
codes up to 64 chips in length for the two modes. Address-
es 44
H
to 4B
H
contain the binary Transmitter Acquisi-
tion/Preamble Symbol PN code chip values, where the
configuration of the stored bits is as shown in Table 20.
The length, N, of the Acquisition/Preamble symbol code is
set by the value of (N-1) stored in bits 5-0 of address 43
H
.
An internal counter begins the transmission with the PN
code chip corresponding to that value. The last chip trans-
mitted per symbol is then code chip 0. Note that this con-
vention agrees with that used for the Z87200’s PN
Matched Filter: for a code of length N, code chip (N-1) will
be the first chip transmitted and will first be processed by
Tap 0 of the PN Matched Filter; the last chip per symbol to
be transmitted, however, will be chip 0, and at that time
chip (N-1) will be processed by Tap (N-1) and chip 0 by
Tap 0 to achieve peak correlation. Operation with the sub-
sequent data symbols is analogous.
Table 21. Acquisition/Preamble Symbol Codes
Addr 4B
H
, Bits 7-0
Code Bits 63-56
Addr 45
H
, Bits 7-0
Code Bits 15-8
Addr 44
H
, Bits 7-0
Code Bits 7-0
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