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參數資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 35/54頁 |
| 文件大?。?/td> | 449K |
| 代理商： | Z87200 |
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Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-35
4
Saturation protection is implemented for those cases when
the Frequency Discriminator output signal level overflows
the scaled range selected for the Loop Filter. When the
scaled value range is exceeded, the saturation protection
limits the output word to the maximum or minimum value
of the range according to whether the positive or negative
boundary was exceeded.
Address 34
H
:
Bits 4-0 — K2 Gain Value
Bits 4-0 control the gain factor K2 within the Loop Filter.
The gain factor multiplies the signal before the K2 accumu-
lator by a value of 2
n
, where n is the 5-bit K2 Gain Value.
The value must range from 0 to 21 (15
H
) as shown in Table
15.
Bit 5 — K2 On
This bit enables or disables the K2 path of the Loop Filter.
Setting this bit low resets the K2 accumulator and keeps it
reset; setting this bit high enables the path and turns on
K2.
Bit 6 — Carry In One Half
When this bit is set high, the value of 1/2 of an LSB is add-
ed to the accumulator of the K2 path of the Loop Filter
each symbol period. This function can be useful in cases
where the scale and gain functions that precede the accu-
mulator produce quantized values with significant error. In
such cases, the processing of two’s complement numbers
by the accumulator will compound the error over time.
Since truncation of two’s complement numbers leads to a
negative bias of 1/2 of an LSB when the error is random,
adding 1/2 of an LSB per symbol can compensate by av-
eraging the error to zero.
When bit 6 of address 34
H
is set high, a value of 1/2 will be
added to the accumulator input each symbol cycle; when
it is low, a zero will be added.
Address 35
H
:
Bits 4-0 — K1 Gain Value
Bits 4-0 control the gain factor K1 within the Loop Filter.
The gain factor multiplies the signal by a value of 2
n
, where
n is the 5-bit K1 Gain Value. The value must range from 0
to 21 (15
H
), as shown in Table 16.
Bit 5 — K1 On
This bit enables or disables the K1 path of the Loop Filter.
Setting this bit low disables the K1 path; setting this bit high
enables the path and turns on K1.
Bit 6 — Freeze Loop
This bit enables the Loop Filter to be held constant during
symbol cycles, thereby fixing the output frequency of the
NCO at the value established by the Loop Filter when bit 6
was set high. This function can be useful in cases where a
carrier offset has been tracked by the Loop Filter and ad-
ditional Doppler offsets are to be ignored.
When this bit is set high, it freezes the output of the Loop
Filter; when it is set low, the Loop Filter is enabled and pro-
cesses the frequency error information in the usual way.
Table 16. K2 Gain Values
Bits 4-0
00
H
01
H
14
H
15
H
Gain in K2 Path
2
0
2
1
2
20
2
21
Table 17. K1 Gain Values
Bits 4-0
00
H
01
H
14
H
15
H
Gain in K1 Path
20
21
2
20
2
21
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