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參數(shù)資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 449K |
| 代理商： | Z87200 |
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Z87200
Spread-Spectrum Transceiver
Zilog
4-26
DS96WRL0400
OUTPUT SIGNALS
(Continued)
pairs. Note that, when the Z87200 is operated in burst
mode, the first bit of RXQOUT in each burst will be invalid.
/RXDRDY (Pin 54)
Receiver Data Ready Bar.
/RXDRDY is provided as a re-
ceiver timing signal. /RXDRDY is normally set high and
pulses low during the baseband sampling clock cycle
when a new RXOUT signal is generated.
RXSPLPLS (Pin 53)
Receiver Sample Pulse.
RXSPLPLS is an output timing
signal that provides internal timing information to the user.
RXSPLPLS is the internally generated baseband sampling
clock, referenced either externally or internally according
to the setting of bit 0 of address 01
H
. All receiver functions,
excluding those in the Downconverter, trigger internally on
the rising edge of RXSPLPLS.
RXSYMPLS (Pin 52)
Receiver Symbol Pulse.
RXSYMPLS is an output signal
that provides the user internal timing information relative to
the detection/correlation of symbols. Symbol information
from the PN Matched Filter, DPSK Demodulator, and Out-
put Processor is transferred on the rising edge of RXS-
PLPLS preceding the falling edge of RXSYMPLS.
RXACTIVE (Pin 83)
Receiver Active.
A high level on RXACTIVE indicates that
the receiver has detected an Acquisition/Preamble symbol
and is currently receiving data symbols. RXACTIVE will be
set high one bit period before the first rising edge of
/RXDRDY, indicating that the first data bit is about to ap-
pear at the RXOUT, RXIOUT, and RXQOUT pins. RXAC-
TIVE will be set low immediately following the last rising
edge of /RXDRDY, indicating that the last data bit of the
burst has been output at the RXOUT, RXIOUT, and RX-
QOUT pins. RXTEST
7-0
(Pins 41-48)
These pins provide access to 16 test points within the re-
ceiver as shown in The pin outputs are selected according
to the value in bits 3-0 of address 38
H
and the assignments
shown in When one of these 4-bit values is written into ad-
dress 38
H
, the corresponding function becomes available
at the RXTEST
7-0
outputs. The RXTEST
7-0
bus is a tri-
state bus and is controlled by the OEN input. Note that the
validity of the RXTEST
7-0
outputs at RXIFCLK speeds
greater than 20 MHz is dependent on the output selected:
outputs that change more rapidly than once per symbol
may be indeterminate.
Table 4. Receiver Test Functions
RXTEST
7-0
Output
Bit 4
Bits 3-0 of 38
H
0
H
1
H
2
H
3
H
4
H
5
H
6
H
7
H
8
H
9
H
A
H
B
H
C
H
D
H
E
H
F
H
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
MFIN2-0 Matched Filter I Input
Bit 1
Bit 0
MFQIN 2-0 Matched Filter Q Input
Pk-Power
9-2
MF Peak Magnitude Output (Changes Once Per Symbol)
COS
7-0
Cosine Output of NCO (Changes Every Cycle of RXIFCLK)
SIN
7-0
Sine Output of NCO (Changes Every Cycle of RXIFCLK)
DCIOUT
16-9
Downconverter I Channel Output (Changes at RXIFCLK Rate)
DCQOUT
16-9
Downcounter Q Output (Changes at RXIFCLK Rate)
ISUM
9-2
Matched Filter I Output (Changes Twice Per Chip)
QSUM
9-2
Matched Filter Q Output (Changes Twice Per Chip)
POWER
9-2
MF Magnitude Output (Changes Twice Per Chip)
ISUM
7-0
MF Viewpoint I Output (Changes Twice Per Chip)
QSUM
7-0
MF Viewpoint Q Output (Changes Twice Per Chip)
Pk-ISUM
7-0
MF Peak I Channel Output (Changes Once Per Symbol)
Pk-QSUM
7-0
MF Peak Q Channel Output (Changes Once Per Symbol)
DOT
16-9
Dot Product (Changes Once Per Symbol)
CROSS
16-9
Cross Product (Changes Once Per Symbol)
TXFBK
7-0
Loopback Test Output
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