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參數(shù)資料
| 型號(hào)： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 20/54頁 |
| 文件大?。?/td> | 449K |
| 代理商： | Z87200 |
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Z87200
Spread-Spectrum Transceiver
Zilog
4-20
DS96WRL0400
FUNCTIONAL BLOCKS
(Continued)
a –45
°
signal rotation must be programmed to optimize the
constellation boundaries in the comparison process be-
tween successive symbols. Note also that introduction of a
±
45
°
rotation introduces a scaling factor of 1/
√
2 to the sig-
nal level in the system as discussed in Theory of Opera-
tion, where this factor should be taken into account when
calculating optimum signal levels and viewport settings af-
ter the DPSK Demodulator
Frequency Discriminator and Loop Filter
The Frequency Discriminator uses the Dot and Cross
products discussed above to generate the AFC signal for
the frequency acquisition and tracking loop, as illustrated
in The specific algorithm used depends on the signal mod-
ulation type and is controlled by the setting of bit 2 of ad-
dress 33
H
. When bit 2 is set low, the Frequency Discrimi-
nator circuit is in BPSK mode and the following algorithm
is used to compute the Frequency Discriminator (FD) func-
tion:
FD = Cross x Sign[Dot],
where Sign[.] represents the polarity of the argument.
When bit 2 is set high, the discriminator circuitry is in
QPSK mode and the carrier discriminator function is in-
stead calculated as:
FD = (Cross x Sign[Dot]) – (Dot x Sign[Cross]).
In both cases, the Frequency Discriminator function pro-
vides an error signal that reflects the change in phase be-
tween successive symbols. With the symbol period known,
the error signal can equivalently be seen as a frequency
error signal. As a practical matter, the computation of the
Frequency Discriminator function results in a 17-bit signal,
and a programmable saturation protected viewport is pro-
vided to select the desired output bits as the 8-bit input to
the Loop Filter Block. The viewport is controlled by the val-
ue stored in bits 7-4 of address 33
H
.
The Loop Filter is implemented with a direct gain (K1) path
and an integrated or accumulated (K2) path to filter the
Frequency Discriminator error signal and correct the fre-
quency tracking of the Downconverter. The order of the
Loop Filter transfer function can be set by enabling or dis-
abling the K1 and K2 paths, and the coefficient values can
be adjusted in powers of 2 from 2
0
to 2
21
. The Loop Filter
transfer function is:
Transfer Fn. = K1 + 1/4 K2
Figure 8. DPSK Demodulator I and Q Channel Processing
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| Z8720020FSG | 功能描述:IC SS MODEM 100-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,140 系列:AU 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:CAN 電源電壓:5.3 V ~ 27 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SO 包裝:管件 其它名稱:935267940512AU5790D14AU5790D14-ND |
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