參數(shù)資料
型號(hào): Z87200
廠商: ZILOG INC
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 7/54頁(yè)
文件大小: 449K
代理商: Z87200
Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-7
4
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to ab-
solute maximum rating conditions for extended period may
affect device reliability.
D.C. CHARACTERISTICS
Operating Conditions: V
DD
= 5.0V
±
5%, V
SS
= 0V
Symbol
Parameter
Range
Units
°
C
Volts
T
V
V
I
I
T
STG
Storage Temperature
(max)Supply Voltage on V
(max)
Input Voltage
DC Input Current
Operating
Temperature (Ambient)
–55 to +150
–0.3 to + 7
–0.3 to V
±
10
0 to +70
DD
DD
I
DD
+0.3 Volts
mA
°
A
C
T
A
= 0
°
to +70
°
C
Typ
Symbol
Parameter
Min
Max
1.0
@ 25
°
C
Units
mA
Conditions
I
DDQ
Supply Current,
Quiescent
Supply Current,
Operational
Static, no clock
I
DD
380
170
[Note]
mA
mA
f
f
Logic ‘1’
RXIFCLK
= 45.056 MHz
= 20 MHz
RXIFCLK
V
IH
(min)
High Level Input
Voltage
Low Level Input Voltage
High Level Input
Current
Low Level Input Current
0.7V
DD
V
DD
+.3
2.6
Volts
V
IL
(min)
I
IH
(min)
V
SS
–.3
0.2V
DD
10
1.5
Volts
μ
A
Logic ‘0’
All inputs, V
IN
= V
DD
I
IL
(max)
–10
μ
A
TXIFCLK, RXIFCLK,
/RESET only, V
IN
= V
SS
All other inputs, V
IN
=
V
SS
I
O
= –2.0 mA, all
outputs
I
O
= +2.0 mA, all
outputs
V
OUT
= V
DD
, V
DD
= max
I
IL
(max)
Low Level Input Current
–130
–15
–45
μ
A
V
OH
(min)
High Level Output
Voltage
Low Level Output
Voltage
Output Short Circuit
Current
Input Capacitance
Output Capacitance
V
DD
–0.4
Volts
V
OL
(max)
0.4
0.1
Volts
I
OS
20
130
65
mA
C
C
OUT
Notes:
1. The operational supply current depends on how the Z87200 is configured.
Typical current consumption can be approximated as follows:
2. I
DD
=5xf
RXIFCLK
+13 x f
CHIP
mA,
3. where f
RXIFCLK
is the frequency of RXIFCLK and f
CHIP
is the PN chip rate,
both in MHz.
2
pF
pF
All inputs
All outputs
4
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