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參數(shù)資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 34/54頁 |
| 文件大?。?/td> | 449K |
| 代理商： | Z87200 |
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Z87200
Spread-Spectrum Transceiver
Zilog
4-34
DS96WRL0400
CONTROL REGISTERS
(Continued)
When RXMABRT is set low, a rising edge on bit 0 of ad-
dress 32
H
will execute the abort function. The function can
also be performed by means of the RXMABRT input. The
RXMABRT input and bit 0 of address 32
H
are logically
ORed together so that, when either one is held low, a rising
edge on the other triggers the abort function. The second
rising edge of the internal baseband sampling clock that
follows a rising edge of this bit will execute the abort and
also clear the symbols-per-burst, samples-per-symbol,
and missed-detects-per-burst counters. The counters will
be reactivated on the detection of the next Acquisition/Pre-
amble symbol or by a manual detect signal.
Demodulator Registers
Address 33
H
:
Bits 1-0 — Signal Rotation Control
These bits control the function of the Signal Rotation Block
used in demodulation of the differentially encoded BPSK,
QPSK, or
π
/4 QPSK signals. The previous symbol will be
rotated in phase with respect to the current symbol as
shown in Table 14, where I
OUT
and Q
OUT
are the I and Q
channel outputs of the Signal Rotation Block and I
IN
and
Q
IN
are the inputs. The normal settings are 0 X (no rota-
tion) for BPSK and
π
/4 QPSK signals and 1 1 (–45
°
rota-
tion) for conventional QPSK signals.
Bit 2 — Not Used
Bit 2 of address 33
H
is not used and must always be set
low (0).
Bit 3 — Loop Clear Disable
The setting of this bit determines whether the Loop Filter’s
K2 accumulator is reset or not when the Z87200 receiver
function is turned off when the input signal MRXEN is set
low.
When bit 3 is set low, the Loop Filter’s K2 accumulator will
be reset to zero whenever MRXEN is set low to disable the
receiver function. When bit 3 is set high, this function is dis-
abled and the contents of the accumulator are not affected
when MRXEN transitions from high to low. The optimum
setting of this bit will depend on the stability of the oscilla-
tors used for carrier generation and frequency translation
in the system and the length of the period between bursts.
If the oscillators are stable and the period between bursts
is not very long, the optimum setting of this bit will be low
so that at the start of each burst the tracking loop will re-
sume from its state at the end of the previous burst. If the
oscillators are not stable or if the period between bursts is
long with respect to the oscillators’ stability, then the opti-
mum setting may be high so that the tracking loop will re-
start from its initial state at the start of each burst.
Bits 7-4 — AFC Viewport Control
The Z87200 incorporates viewport (data selector) circuitry
to select any eight consecutive bits from the 17-bit output
of the Frequency Discriminator as the 8-bit input to the
Loop Filter block to implement the Z87200’s AFC function.
The unsigned value, n, of bits 7-4 of address 33
H
deter-
mines the 8-bit input to the Loop Filter as the 17-bit Fre-
quency Discriminator output divided by 2
n
. Equivalently,
bits 7-4 control the viewport of the Frequency Discrimina-
tor output as shown in Table 14.
Table 14. Signal Rotation Control
Bits 1,0
0, X
1,0
1,1
I
OUT
I
IN
I
IN
-Q
IN
I
IN
+ Q
IN
Q
OUT
Q
IN
Q
IN
+I
IN
Q
IN
-I
IN
Resulting
Rotation
No rotation
+45
°
rotation
-45
°
rotation
Table 15. AFC Viewport Control
Bits 7-4
0
H
1
H
2
H
3
H
8
H
9
H
A
H
-F
H
Discrim. bits output to Loop Filter
7-0
8-1
9-2
10-3
15-8
16-9
Not used
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