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參數(shù)資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 36/54頁 |
| 文件大?。?/td> | 449K |
| 代理商： | Z87200 |
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Z87200
Spread-Spectrum Transceiver
Zilog
4-36
DS96WRL0400
CONTROL REGISTERS
(Continued)
Output Processor Control Registers
Address 36
H
:
Bit 0 — Reverse I and Q
In QPSK mode, the order in which the received I and Q bit
information is output may be reversed by setting this bit
high. This function has the effect of interchanging I and Q
channels. Normally, when this bit is set low, the I-channel
bit will precede the Q-channel bit in each symbol period.
When bit 0 is set high, the Q-channel bit will precede the I-
channel bit each symbol period.
Bit 1 — BPSK Enable
This bit configures the Output Processor to output either
one bit per symbol (BPSK mode) or two bits per symbol
(QPSK mode). In addition, it enables the user to output the
I-channel information only or the Q-channel information
only, depending on the value of bit 0. Table 18 shows the
configuration of the output processor for all combinations
of the values of bits 0 and 1.
Bit 1 also sets the Frequency Discriminator into either
BPSK or QPSK mode. The Z87200 receiver uses Dot and
Cross product results generated within the DPSK Demod-
ulator to develop the error signal used to form a closed-
loop AFC for carrier frequency acquisition and tracking.
When bit 1 is set high, the discriminator circuitry is in BPSK
mode and the Frequency Discriminator function is calcu-
lated as:
Cross
16-0
x Dot
MSB
.
When bit 1 is set low, the discriminator circuitry is in QPSK
mode and the Frequency Discriminator function is calcu-
lated as:
(Cross
16-0
x Dot
MSB
) – (Dot
16-0
x Cross
MSB
).
Bit 2 – Invert Output
This bit inverts the output bits of both the I and Q Chan-
nels. The inversion will occur at the output pins RXOUT,
RXIOUT, and RXQOUT.
When this bit is set low, the outputs are not inverted; when
it is set high, the outputs are inverted.
Output Processor Control Registers
Address 37
H
:
Bit 0 — NCO Enable
The function of this bit is to allow the power consumed by
the operation of the NCO circuitry to be minimized when
the Z87200 is not receiving. The NCO can also be disabled
while the Z87200 is transmitting provided that the
Z87200’s on-chip BPSK/QPSK modulator is not being
used. With the instantaneous acquisition properties of the
PN Matched Filter, it is often desirable to shut down the re-
ceiver circuitry to reduce power consumption, resuming re-
ception periodically until an Acquisition/Preamble symbol
is acquired. Setting bit 0 low holds the NCO in a reset
state; setting bit 0 high then reactivates the NCO, where it
is necessary to reload the frequency control word into the
NCO. Note that this bit operates independently of bits 1
(Transmitter Enable) and 2 (Receiver Enable), where
those bits have similar control over the transmit and re-
ceive circuitry, respectively.
Bit 0 of address 37
H
performs the same function as MN-
COEN, and these two signals are logically ORed together
to form the overall control function. When bit 0 is set low,
MNCOEN controls the activity of the NCO circuitry and,
when MNCOEN is set low, bit 0 controls the activity of the
NCO circuitry. When either bit 0 or MNCOEN (whichever
is in control, as defined above) goes low, a reset sequence
occurs on the following RXIFCLK cycle to virtually disable
all of the NCO circuitry, although the user programmable
control registers are not affected by the power down se-
quence. Upon reactivation (when either MNCOEN or bit 0
of address 37
H
return high), the NCO must be reloaded
with frequency control information either by means of the
MFLD input or by writing 01
H
into address 00
H
.
Bit 1 — Transmitter Enable
A rising edge on this bit causes the transmit sequence to
begin so that the Z87200 first transmits a single Acquisi-
tion/Preamble symbol followed by data symbols. Bit 1 of
address 37
H
should be set low after the last symbol has
been transmitted to minimize power consumption of the
transmitter circuit. Bit 1 of address 37
H
operates indepen-
dently of bits 2 and 0, where those bits have similar control
over the receive and NCO circuitry, respectively.
Table 18. Output Processor Modes
Bit 1
0
Bit 0
0
Output Processor Mode
QPSK mode with I-Channel Bit
Preceding Q-Channel Bit
QPSK mode with Q-Channel Bit
Preceding I-Channel Bit
BPSK mode with I-Channel
Information Output
BPSK mode with Q-Channel
Information Output
0
1
1
0
1
1
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