參數(shù)資料
型號(hào)： Z87200
廠商： ZILOG INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 24/54頁(yè)
文件大小： 449K
代理商： Z87200
Z87200
Spread-Spectrum Transceiver
Zilog
4-24
DS96WRL0400
FUNCTIONAL BLOCKS
(Continued)
TXMCHP (Pin 19)
Transmit Manual Chip Pulse.
TXMCHP enables the user
to provide the PN chip rate clock pulses from an external
source. This feature is useful in cases where a specific
chip rate is required that cannot be derived by the internal
clock generator which generates clocks of integer sub-
multiples of TXIFCLK. The signal is internally synchro-
nized to TXIFCLK to avoid intrinsic race or hazard timing
conditions.
When bit 2 of address 40
H
is set high, a rising edge on
TXMCHP will generate the chip clock to the differential en-
coder and the following circuitry (Acquisition/Preamble
and Data Symbol PN spreaders, etc.). The rising edge of
TXMCHP is synchronized internally so that, on the third
rising edge of TXIFCLK following the rising edge of TXM-
CHP, the PN code combined with the differentially encod-
ed signal will change, generating the next chip.
TXIFCLK (Pin 14)
Transmitter I.F. Clock.
TXIFCLK is the master clock of
the transmitter. All transmitter clocks, internal or external,
are generated or synchronized internally to the rising edge
of TXIFCLK. The rate of TXIFCLK must be at least twice
the transmit PN chip rate. It may be convenient to use the
same external signal for both TXIFCLK and RXIFCLK, in
which case the frequency of TXIFCLK will be at least four
times the PN chip rate as required for RXIFCLK. Moreover,
if the Z87200’s on-chip BPSK/QPSK Modulator is to be
used, TXIFCLK and RXIFCLK must be identical and
should not exceed 20 MHz.
MFLD (Pin 85)
Manual Frequency Load.
MFLD is used to load a fre-
quency control value into the NCO. The NCO may be load-
ed in various ways, but MFLD provides a synchronized ex-
ternal method of updating the NCO, while the other
methods involve setting bit 0 of address 00H or using the
programmable loop filter timing circuitry. MFLD is internal-
ly synchronized to RXIFCLK to avoid internal race or haz-
ard timing conditions.
The MFLD input and bit 0 of address 00H are logically
ORed together so that, when either one is held low, a rising
edge on the other triggers the frequency load function
manually. The rising edge of MFLD is synchronized inter-
nally so that, on the sixth following rising edge of RXIF-
CLK, the frequency control word is completely registered
into the NCO accumulator. The frequency load command
must not be repeated until the six RXIFCLK cycle delay is
completed.
/WR (Pin 28)
Write Bar.
/WR is used to latch user-configurable informa-
tion into the control registers. It is important to note that the
control registers are transparent latches while /WR is set
low. The information will be latched when /WR returns
high. DATA
7-0
and ADDR
6-0
should be stable while /WR is
set low in order to avoid undesirable effects.
DATA
7-0
(Pins 20-27)
Data Bus.
DATA
7-0
is an 8-bit microprocessor interface
bus that provides access to all internal control register in-
puts for programming. DATA
7-0
is used in conjunction with
the ADDR
6-0
and /WR signals to set the values of the con-
trol registers.
ADDR
6-0
(Pins 32-38)
Address Bus.
ADDR
6-0
is a 7-bit address bus that selects
the control register location into which the information pro-
vided on the DATA
7-0
bus will be written. ADDR
6-0
is used
in conjunction with /WR and DATA
7-0
to write the informa-
tion into the registers.
/CSEL (Pin 29)
Chip Select Bar.
/CSEL is provided to enable or disable
the microprocessor operation of the Z87200. When /CSEL
is set high, the ADDR
6-0
and /WR become disabled and
have no effect on the device. When /CSEL is set low, the
device is in its normal mode of operation and ADDR
6-0
and
/WR are active.
/OEN (Pin 49)
Output Enable Bar.
/OEN is provided to enable or disable
the RXTEST
7-0
output bus. When /OEN is set high, the
RXTEST
7-0
bus will have a high impedance, allowing it to
be connected to other busses, such as DATA
7-0
. When
/OEN is set low, the RXTEST
7-0
bus will be active, allowing
the RXTEST function selected to be accessed.
/RESET (Pin 16)
Reset Bar.
/RESET is the master reset of the Z87200,
clearing the control registers as well as the contents within
the receiver, transmitter, and NCO data paths when it is
set low. Setting /RESET high enables operation of the cir-
cuitry.
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