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參數資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 2/54頁 |
| 文件大?。?/td> | 449K |
| 代理商： | Z87200 |
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Z87200
Spread-Spectrum Transceiver
Zilog
4-2
DS96WRL0400
GENERAL DESCRIPTION
(Continued)
tal-to-analog conversion (or, if preferred, the spread base-
band signal may be output to an external modulator).
These transceiver functions have been designed and inte-
grated for the transmission and reception of bursts of
spread data. In particular, the PN Matched Filter has two
distinct PN coefficient registers (rather than a single one)
in order to speed and improve signal acquisition perfor-
mance by automatically switching from one to the other
upon signal acquisition. The Z87200 is thus optimized to
provide reliable, high-speed wireless data communica-
tions.
Symbol-Synchronous PN Modulation
The Z87200 operates with symbol-synchronous PN mod-
ulation in both transmit and receive modes. Symbol-syn-
chronous PN modulation refers to operation where the PN
code is aligned with the symbol transitions and repeats
once per symbol. By synchronizing a full PN code cycle
over a symbol duration, acquisition of the PN code at the
receiver simultaneously provides symbol synchronization,
thereby significantly improving overall acquisition time.
As a result of the Z87200's symbol-synchronous PN mod-
ulation, the data rate is defined by the PN chip rate and
length of the PN code; that is, by the number of chips per
symbol, where a “chip” is a single “bit” of the PN code. The
PN chip rate, R
c
chips/second, is programmable to as
much as 1/4 the rate of RXIFCLK, and the PN code length,
N, can be programmed up to a value of 64. When operat-
ing with BPSK modulation, the data rate for a PN code of
length N and PN chip rate R
C
chips/sec is R
operating with QPSK modulation (or
ternal modulator), two bits of data are transmitted per sym-
bol, and the data rate for a PN code of length N and PN
chip rate R
c
chips/sec is 2R
c
/N bps. Conversely, for a giv-
en data rate R
b
bps, the length N of the PN code defines
the PN chip rate R
c
as N x R
b
x R
b
)/2 chips/sec for QPSK.
C
/N bps. When
/4 QPSK with an ex-
π
chips/sec for BPSK or as (N
The data rate R
not generally be arbitrarily chosen. United States FCC Part
15.247 regulations require a minimum processing gain of
10 dB for unlicensed operation in the Industrial, Scientific,
and Medical (ISM) bands, implying that the value of N must
be at least 10. To implement such a short code, a Barker
code of length 11 would typically be used in order to obtain
desirable auto- and cross-correlation properties, although
compliance with FCC regulations depends upon the over-
all system implementation. The Z87200 further includes
transmit and receive code overlay generators to insure
that signals spread with such a short PN code length pos-
sess the spectral properties required by FCC regulations.
b
and the PN code length N, however, can-
The receiver clock rate established by RXIFCLK must be
at least four times the receive PN spreading rate and is lim-
ited to a maximum speed of 45.056 MHz in the 45 MHz
Z87200 and 20.0 MHz in the 20 MHz Z87200. The ensuing
discussion is in terms of the 45 MHz Z87200, but the nu-
merical values may be scaled proportionately for the 20
MHz version. As a result of the maximum 45.056 MHz RX-
IFCLK, the maximum supported PN chip rate is 11.264
Mchips/second. When operating with BPSK modulation,
the maximum data rate for a PN code of length N is
11.264/N Mbps. When operating with QPSK modulation
(or
π
/4 QPSK with an external modulator), two bits of data
are transmitted per symbol, and the data rate for a PN
code of length N is 22.528/N Mbps. Conversely, for a given
data rate R
b
, the length N of the PN code employed must
be such that the product of N x R
Mchips/sec (for BPSK) or 22.528 Mchips/sec (for QPSK).
For the 45 MHz Z87200, then, a PN code length of 11 im-
plies that the maximum data rate that can be supported in
compliance with the processing gain requirements of FCC
regulations is 2.048 Mbps using differential QPSK. Note
again, however, that FCC compliance using the Z87200
with a PN code of length 11 depends upon the overall sys-
tem implementation.
b
is less than 11.264
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