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參數(shù)資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 16/54頁 |
| 文件大小： | 449K |
| 代理商： | Z87200 |
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Z87200
Spread-Spectrum Transceiver
Zilog
4-16
DS96WRL0400
FUNCTIONAL BLOCKS
(Continued)
Frequency Control Register and NCO
The Z87200 incorporates a Numerically Controlled Oscil-
lator (NCO) to synthesize a local oscillator signal for both
the transmitter’s modulator and receiver’s downconverter.
The NCO is clocked by the master receiver clock signal,
RXIFCLK, and generates quadrature outputs with 32-bit
frequency resolution. The NCO frequency is controlled by
the value stored in the 32-bit Frequency Control Register,
occupying 4 bytes at addresses 03
H
to 06
H
. To avoid de-
structive in-band aliasing, the NCO should not be pro-
grammed to be greater than 50% of RXIFCLK. As desired
by the user, the output of the Z87200 receiver’s Loop Filter
can then be added or subtracted to adjust the NCO’s fre-
quency control word and create a closed-loop frequency
tracking loop. If the receiver is disabled, either manually or
automatically at the end of a burst, the Loop Filter output
correcting the NCO’s Frequency Control Word is disabled.
When simultaneously operating both the transmitter and
receiver, however, the receiver’s frequency tracking loop
affects the NCO signals to both the receive and transmit
sides, a feature which can either be used to advantage in
the overall system design or must be compensated in the
programming of the Z87200 or in the system design.
Downconverter
The Z87200 incorporates a Quadrature (Single Sideband)
Downconverter which digitally downconverts the sampled
and digitized receive I.F. signal to baseband. Use of the
Loop Filter and the NCO’s built-in frequency tracking loop
permits the received signal to be accurately downconvert-
ed to baseband.
The Downconverter includes a complex multiplier in which
the 8-bit receiver input signal is multiplied by the sine and
cosine signals generated by the NCO. In Quadrature Sam-
pling Mode, two ADCs provide quadrature (complex) in-
puts I
IN
and Q
IN
, while, in Direct I.F. Sampling Mode, a sin-
gle ADC provides I
IN
as a real input. The input signals can
be accepted in either two’s complement or offset binary
formats according to the setting of bit 3 of address 01
H
. In
Direct I.F. Sampling Mode, the unused RXQIN Q channel
input (Q
IN
) should be held to “zero” according to the ADC
input format selected. The outputs of the Downconverter’s
complex multiplier are then:
I
OUT
=
I
IN
. cos(
ω
t) –
Q
IN
. sin(
ω
t)
Q
OUT
=
I
IN
. s
in
(
ω
t) +
Q
IN
. cos(
ω
t)
where
ω
=
2
π
f
nco
These outputs are fed into the I and Q channel Integrate
and Dump Filters. The Integrate and Dump Filters allow
the samples from the complex multiplier (at the I.F. sam-
pling rate, the frequency of RXIFCLK) to be integrated over
a number of sample periods. The dump rate of these filters
(the baseband sampling rate) can be controlled either by
an internally generated dump clock or by an external input
signal (RXMSMPL) according to the setting of bit 0 of ad-
dress 01
H
. Note that, while the receiver will extract exact
PN and symbol timing information from the received sig-
nal, the baseband sampling rate must be twice the nominal
PN chip rate for proper receiver operation and less than or
equal to one-half the frequency of RXIFCLK. If twice the
PN chip rate is a convenient integer sub-multiple of RXIF-
CLK, then an internal clock can be derived by frequency di-
viding RXIFCLK according to the divisor stored in bits 5-0
of address 02
H
; otherwise, an external baseband sampling
clock provided by RXMSMPL must be used.
The I.F. sampling rate, the baseband sampling rate, and
the input signal levels determine the magnitudes of the In-
tegrate and Dump Filters’ accumulator outputs, and a pro-
grammable viewport is provided at the outputs of the Inte-
grate and Dump Filters to select the appropriate output bits
as the 3-bit inputs to the PN Matched Filter. The viewport
circuitry here and elsewhere within the Z87200’s receiver
is designed with saturation protection so that extreme val-
ues above or below the selected range are limited to the
correct maximum or minimum value for the selected view-
port range. Both viewports for the I and Q channels of the
Integrate and Dump Filters are controlled by the values
stored in bits 7-4 of address 01
H
.
Receiver PN Code Register and PN Matched
Filter
As discussed for the Z87200 transmitter, the Z87200 re-
ceiver is designed for burst signal operation in which each
burst begins with a single Acquisition/Preamble symbol
and is then followed by data symbols for information trans-
mittal. Complementing operation of the Z87200’s transmit-
ter, two separate and independent PN codes may be em-
ployed in the receiver’s PN Matched Filter, one for
despreading the Acquisition/Preamble symbol, and one for
the information data symbols. The code lengths are com-
pletely independent of each other and can be each up to
64 chips long. A block diagram of the PN Matched Filter is
shown in Figure 3.
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