參數(shù)資料
型號(hào): Z87200
廠(chǎng)商: ZILOG INC
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: CAP 0.047UF 100V 10% X7R AXIAL TR-14
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 49/54頁(yè)
文件大?。?/td> 449K
代理商: Z87200
Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-49
4
at the transmitter is performed by processing the sum fre-
quency of the local oscillator and the modulator; when the
mixing at the receiver is performed by subtracting the local
oscillator from the incoming signal; and when the in-phase
and quadrature inputs into the I and Q analog-to-digital
converters are correctly connected such that the in-phase
component leads the quadrature component by 90
°
. Un-
der these conditions, bit 0 of address 36
H
should be set to
0; otherwise, the I and Q channels may need to be re-
versed at the DPSK demodulator (by setting bit 0 of ad-
dress 36
H
to 1) in order to achieve proper demodulation.
Frequency Error Signal Generation
The frequency discriminator function or error signal is gen-
erated based on the Dot and Cross products. The objec-
tive is an error signal that is proportional to the sine of the
phase difference between the present and prior symbol af-
ter correcting for the estimated phase increments due to
data modulation. In the Z87200 Frequency Discriminator,
the frequency error is calculated through a decision-direct-
ed cross-product algorithm and is then used with the Loop
Filter to correct the NCO frequency. Assuming an input
sin(k), where:
s
in
(k) =
I(k) + j Q(k),
the algorithm calculates the frequency discriminator func-
tion for DBPSK, s
AFC/BPSK
(k), as:
S
AFC/BPSK
(k)=SIGN[Dot(k)]*Cross(k)
=SIGN[Dot(k)]*A(k)*A(k-1)*sin((k)-(k-1))
=SIGN[Dot(k)]*A(k)*A(k-1)*sin(
mod(k) +
rot(k))
SIGN[Dot(k)]*A2(k)*cos[
mod(k)]*sin[
rot(k)]
A2(k)*sin[
rot(k)]*
The final result assumes that the amplitude of the signal is
constant over consecutive symbols and shows that the
discriminator function is directly related to the change in
phase between successive symbols. Since the interval be-
tween successive symbols is fixed, the discriminator func-
tion can be interpreted as a frequency error signal.
For DQPSK signals, the Z87200 computes the discrimina-
tor function S
AFC/QPSK
(k) as:
S
AFC/QPSK(
k)=SIGN[Dot(k)] Cross(k) - SIGN[Cross(k)]
Dot(k),
where the above expression can be reduced to the same
as for DBPSK,
S
AFC/QPSK
(k)
A2(k)*sin(
rot(k)).
BPSK/QPSK Modulation
The Z87200 incorporates a Direct Digital Synthesizer
(DDS) to implement its on-chip BPSK/QPSK modulator. In
the Z87200 design, the NCO and thus the sampling clock
for the modulator is driven by fRXIFCLK; for this reason,
both TXIFCLK and RXIFCLK must be common if the on-
chip BPSK/QPSK modulator is to be used. The
BPSK/QPSK modulator can then be used to generate the
transmit output signal at a programmable IF frequency,
thereby eliminating the need for an external modulator.
Because it is a sampled data system like the Downconvert-
er of the Z87200, however, care must be taken to ensure
that the results of aliasing do not adversely affect the out-
put transmit signal.
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