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參數(shù)資料
| 型號： | Z87200 |
| 廠商： | ZILOG INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | CAP 0.047UF 100V 10% X7R AXIAL TR-14 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 33/54頁 |
| 文件大?。?/td> | 449K |
| 代理商： | Z87200 |
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Z87200
Zilog
Spread-Spectrum Transceiver
DS96WRL0400
4-33
4
sert missed detect pulses; when set low, normal operation
will be enabled whereby data symbols are automatically
processed immediately following detection of an Acquisi-
tion/Preamble symbol.
Bit 3 — Bypass Max. Power Selector
The Z87200’s receiver acquisition and tracking circuitry in-
cludes a function that continuously selects the highest es-
timated power level out of the three most recent consecu-
tive estimated power levels from the PN Matched Filter. As
the contents of the sliding 3-sample window change each
cycle of the baseband sampling clock, a new determina-
tion of the highest power level is made from the current set
of the three most recent power level values. The correlated
I and Q channel values within the 3-sample window corre-
sponding in time to the highest observed power level are
then available to be processed in the demodulator.
This function assures that, within any 3-sample period, the
I and Q channel values corresponding to the highest esti-
mated power level will be selected over the two other pairs
of correlated values even if the estimated power levels of
the other pairs exceed the programmed threshold. The
Maximum Power Selector is used in normal operation of
the Z87200 so that the tracking algorithm discriminates by
estimated power levels rather than exact timing intervals,
thereby allowing the receiver to adjust to dynamic changes
of the symbol phase. In cases where specific correlation
values are desired regardless of their associated power
level, bit 3 of address 30
H
enables the 3-sample power dis-
criminator to be bypassed, thereby making the outputs of
the PN Matched Filter available directly to the demodula-
tor.
When this bit is set high, the Maximum Power Selector is
bypassed; when it is set low, the Selector is enabled,
where this is the normal operating mode.
Bit 4 — Half Symbol Pulse Off
The Z87200 generates two bit clock pulses per symbol
when operating in QPSK mode, one at the mid-point of
each symbol and one at the end of each symbol. These
clocks are used by the Output Processor to manage data
flow.
When this bit is set high, the mid-point pulse is sup-
pressed; when it is set low, the device operates in its nor-
mal mode. This function is primarily used for test purposes
and should not normally be used.
Bit 5 — Missed Detects Per Burst Off
To monitor the quality of the received burst data symbols,
the Symbol Tracking Processor keeps track of the cumu-
lative number of received data symbols per burst whose
estimated correlation power level did not exceed the spec-
ified Data Symbol Threshold value. When the accumulat-
ed number of missed detects equals the Missed Detects
per Burst Threshold value stored in address 2F
H
, the de-
vice will terminate the reception of the current burst with
the next missed detect and return to acquisition mode to
await the next burst.
When bit 5 is set low, the “missed detect” function operates
normally; when set high, this function is disabled, allowing
the device to be operated until the end of the specified data
burst even when the number of “missed detects” exceeds
the Missed Detects per Burst Threshold.
Bit 6 — Receiver Symbols Per Burst Off
The data stored in addresses 2E
H
and 3A
H
defines the
number of data symbols per burst that will be processed by
the receiver. This unsigned value must range from 3 to
65,535 (0003
H
to FFFF
H
), and the number of data symbols
per burst will be this value minus 2. Once the number of
data symbols processed by the receiver exceeds this num-
ber, the burst is assumed to have ended and the receiver
will immediately return to acquisition mode.
When bit 6 is set high, the function is disabled, providing
an option to track data symbols under external control for
bursts of more than 65,533 data symbols or indefinitely for
continuous transmission; when set low, the function will
operate normally as defined by the value stored in ad-
dresses 2E
H
and 3A
H
.
Address 31
H
:
Bit 0 — Manual Detect Pulse
This bit provides the user a means to externally generate
symbol timing, bypassing and overriding the internal sym-
bol power estimation and tracking circuitry. This function
may be useful in applications where the dynamic charac-
teristics of the transmission environment require unusual
adjustments to the symbol timing.
When bit 0 of address 30
H
is set high (Manual Detect En-
able) and when RXMDET is low, a rising edge on this bit
will generate a detect pulse. The function can also be per-
formed by means of the RXMDET input signal. Bit 0 of ad-
dress 31
H
and the RXMDET input are logically ORed to-
gether so that, when either one is held low, a rising edge
on the other triggers the manual detect function. The rising
edge of this bit is synchronized internally so that on the
second rising edge of the baseband sampling clock that
follows, the rising edge of bit 0 will transfer the I and Q
channel correlated output values of the PN Matched Filter
to the DPSK Demodulator.
Address 32
H
:
Bit 0 — Receiver Manual Abort
This bit enables the user to manually force the Z87200 to
cease reception of the present burst of data symbols and
prepare for acquisition of a new burst. This function can be
used to reset the receiver and prepare to receive a priority
transmission signal under precise timing control, giving the
user the ability to control the current state of the receiver
as needed.
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