TABLE 111:
參數(shù)資料
型號(hào)： XRT72L71IQ
廠商： Exar Corporation
文件頁數(shù)： 98/102頁
文件大小： 0K
描述： IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告： XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝： 24
控制器類型： DS3 ATM UNI，透明通道調(diào)幀器
電源電壓： 3.3V
電流 - 電源： 120mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
91
TABLE 111: TX UTOPIA INTERRUPT/STATUS REGISTER
REGISTER 110
TX UTOPIA INTERRUPT/STATUS REGISTER
HEX ADDRESS: 0X6E
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Tx FIFO Reset
R/W
0
0 to 1 transition resets internal FIFO memory and its read-write pointers.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
6
Discard Upon PErr
R/W
0
0: “Transmit UTOPIA” Parity errors do not result in cell discard
1: Cells in which a “Transmit UTOPIA” parity error is detected are discarded.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
5
Tx Parity Error Interrupt
Enable
R/W
0
0: Disables the “Transmit UTOPIA Detection of Parity Error” Interrupt.
1: Enables the “Transmit UTOPIA Detection of Parity Error” Interrupt.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
4
Tx FIFO Overrun Interrupt
Enable
R/W
0
0: Disables the “TxFIFO Overrun” interrupt.
1: Enables the “TxFIFO Overrun” interrupt.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
3
TC Out of Cell Alignment
Interrupt Enable
R/W
0
0: Disables the “Detection of TxRUNT Cell” interrupt.
1: Enables the “Detection of TxRUNT Cell” interrupt.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
2
TP Error Interrupt Status
RUR
0
0: Indicates that the “Detection of Transmit UTOPIA - Parity Error” Interrupt
has NOT occurred since the last read of this register.
1: Indicates that the “Detection of Transmit UTOPIA - Parity Error” Interrupt
has occurred since the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
1
Tx FIFO Interrupt Status
RUR
0
0: Indicates that the “TxFIFO Overrun” Interrupt has NOT occurred since the
last read of this register.
1: Indicates that the “TxFIFO Overrun” Interrupt has occurred since the last
read of this register.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
0
TC OCA Interrupt Status
RUR
0
0: Indicates that the “Detection of TxRUNT Cell” Interrupt has NOT occurred
since the last read of this register.
1: Indicates that the “Detection of TxRUNT Cell” Interrupt has occurred since
the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
TABLE 112: FUTURE USE
REGISTER 111
FUTURE USE
HEX ADDRESS: 0X6F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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