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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
13
82
TCK
I
Test Clock: Boundry Scan clock input.
NOTE: This input pin should be pulled “Low” for normal operation.
83
TMS
I
Test Mode Select: Boundry Scan Mode Select input.
NOTE: This input pin should be pulled “Low” for normal operation.
84
TDI
I
Test Data In: Boundry Scan Test data input.
NOTE: This input pin should be pulled “Low” for normal operation.
85
TDO
O
Test Data Out: Boundry Scan test data output.
86
RLOS
I
Receive LOS (Loss of Signal) Indicator Input (from XRT7300 E3/DS3/
STS-1 Line Interface Unit). This input pin is intended to be connected to the
RLOS (Receive Loss of Signal) output pin of the XRT7300 E3/DS3 /STS-1 Line
Interface IC. The user can monitor the state of this pin by reading the state of Bit
0 (RLOS) within the Line Interface Scan Register (Address = 73h).
If this input pin is “Low”, then it means that the XRT7300 is detecting a sufficient
amount of signal energy on the line, due to the incoming DS3 data-stream. How-
ever, if this input pin is “High”, then it means that the XRT7300 is not detecting a
sufficient amount of signal energy on the line, due to the incoming DS3 data-
stream, and may be experiencing a “Loss of Signal” condition.
For more information on the operation of the XRT7300 E3/DS3/STS-1 Line
Interface Unit IC, please consult the “XRT7300 ” data sheet.
NOTE: Asserting the RLOS input pin will cause the XRT72L71 DS3 UNI to
declare an “LOS” (Loss of Signal) condition. Therefore, this input pin should
not be used as a general purpose input.
87
8KRef
I
8 kHz Reference Clock Input for the PLCP Processors: The Transmit
PLCP processor can be configured to synchronize its PLCP frame processing
to this clock signal. The Transmit PLCP Processor will also use this signal to
compute the trailer nibble stuff opportunities.
NOTES:
1. This input signal is active only if the user has configured the PLCP
Processors to use this signal as their “master clock” signal. The user
can configure the UNI to use this signal by setting TimRefSel[1,0]
(within the UNI Operating Mode Register) to 01.
2. The user should tie this pin to “GND” whenever the XRT72L71 has
been configured to operate in the “Clear-Channel-Framer” Mode.
88
RxLOS
O
Receive DS3 Framer—Loss of Signal Output Indicator: This pin is
asserted when the Receive DS3 Framer encounters 180 consecutive 0’s via
the RxPOS and RxNEG pins. This pin will be negated once the Receive DS3
Framer has detected at least 60 “1s” out of 180 consecutive bits.
89
RxOH
O
Receive Overhead Output Port
All overhead bits, which are received via the "Receive Section" of the Framer
IC; will be output via this output pin, upon the rising edge of RxOHClk.
90
RxOOF
O
Receiver DS3 Framer—“Out of Frame” Indicator: The Receive DS3 Framer-
block will assert this output signal (e.g., pull it “High”) whenever it has declared
an “Out of Frame” (OOF) condition with the incoming DS3 frames. This signal
is negated when the framer correctly locates the F- and M-bits and regains
synchronization with the DS3 frame.
91
GND
***
Ground Signal Pin
PIN DESCRIPTION (CONTINUED)
PIN NO.
SYMBOL
TYPE
DESCRIPTION