參數(shù)資料
型號(hào)： XRT72L71IQ
廠商： Exar Corporation
文件頁數(shù)： 20/102頁
文件大?。?/td> 0K
描述： IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告： XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝： 24
控制器類型： DS3 ATM UNI，透明通道調(diào)幀器
電源電壓： 3.3V
電流 - 電源： 120mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
20
126
TxUClav
O
Transmit UTOPIA Interface—Cell Available Output Pin: This output pin
supports data flow control between the ATM Layer processor and the Transmit
UTOPIA Interface block. The exact functionality of this pin depends upon
whether the UNI is operating in the “Octet Level” or “Cell Level” handshaking
mode.
Octet Level Handshaking: When the Transmit UTOPIA Interface block is
operating in the octet-level handshaking mode, this signal is negated (toggles
“Low”) when the TxFIFO is not capable of handling four more write operations;
by the ATM Layer processor to the Transmit UTOPIA Interface block. This sig-
nal will be asserted when the TxFIFO is capable of receiving four or more
write operations of ATM cell data.
Cell Level Handshaking: When the Transmit UTOPIA Interface block is oper-
ating the cell-level handshaking mode, this signal is asserted (toggles “High”)
when the TxFIFO is capable of receiving at least one more full cell of data
from the ATM Layer processor. This signal is negated, if the TxFIFO is not
capable of receiving one more full cell of data from the ATM Layer processor.
Multi-PHY Operation: When the UNI chip is operating in the Multi-PHY
mode, this signal will be tri-stated until the TxUClk cycle following the asser-
tion of a valid address on the Transmit UTOPIA Address bus input pins (e.g.,
when the contents on the Transmit UTOPIA Address bus pins match that
within the Transmit UTOPIA Address Register). Afterwards, this output pin will
behave in accordance with the cell-level handshake mode.
NOTE: This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
127
GND
***
Ground Signal Pin.
128
129
130
131
132
133
134
135
TxUData8
TxUData0
TxUData9
TxUData1
TxUData10
TxUData2
TxUData11
TxUData3
I
Transmit UTOPIA Data Bus Input:
Please see description for TxUData15, pin 144.
NOTES:The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
TxUData0 - Transmit UTOPIA Data Bus Input - LSB.
136
VDD
***
Power Supply Pin
137
138
139
140
141
142
143
TxUData4
TxUData12
TxUData5
TxUData13
TxUData6
TxUData14
TxUData7
I
Transmit UTOPIA Data Bus Input:
Please see description for TxUData15 pin 144.
NOTE: The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
144
TxUData15
I
Transmit UTOPIA Data Bus Input—MSB: This input pin, along with
TxUData14 through TxUData0 comprise the Transmit UTOPIA Data Bus input
pins. When the ATM Layer Processor wishes to transmit ATM cell data through
the XRT72L71 DS3 UNI, it must place this data on these pins. The data, on
the Transmit UTOPIA Data Bus is latched into the Transmit UTOPIA Interface
block on the rising edge of TxUClk.
NOTE: The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
145
VDD
***
Power Supply Pin
PIN DESCRIPTION (CONTINUED)
PIN NO.
SYMBOL
TYPE
DESCRIPTION
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