TABLE 98:
參數(shù)資料
型號: XRT72L71IQ
廠商: Exar Corporation
文件頁數(shù): 93/102頁
文件大?。?/td> 0K
描述: IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告: XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝: 24
控制器類型: DS3 ATM UNI,透明通道調(diào)幀器
電源電壓: 3.3V
電流 - 電源: 120mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
包裝: 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
86
TABLE 98: TX CP OAM REGISTER
REGISTER 97
TX CP OAM REGISTER
HEX ADDRESS: 0X61
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Send OAM
Sem
0
A “0” to “1” transitions configures the Transmit Cell Processor to transmit an
OAM cell.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
6
Tx CRC10 Enable
R/W
0
0: OAM Cell CRC-10 Calculation and Insertion are disabled.
1: OAM Cell CRC-10 Calculation and Insertion is enabled. The Transmit
Cell Processor will compute and insert the CRC-10 value within each “out-
bound” OAM cell.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
5-0
Unused
RO
0x00
TABLE 99: TX CP HEC ERROR MASK REGISTER
REGISTER 98
TX CP HEC ERROR MASK REGISTER
HEX ADDRESS: 0X62
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
HEC Error Mask
R/W
0x00
The Transmit Cell Processor block always XORs contents of this register with
the contents of the HEC byte (within each “outbound” ATM cell). This
“XORed” value is then written back into the “HEC” byte field, within each
“outbound” ATM cell; prior to transmission. Setting any of these bit-fields to
“1” introduces error in that specific bit, within each “outbound” HEC byte.
Register must be set to 0x00 for normal operation,
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
TABLE 100: FUTURE USE
REGISTER 99
FUTURE USE
HEX ADDRESS: 0X63
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
TABLE 101: TX CP IDLE CELL PATTERN HEADER BYTE-1
REGISTER 100
TX CP IDLE CELL PATTERN HEADER BYTE-1
HEX ADDRESS: 0X64
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Pattern 1
R/W
0x00
Contains pattern for the first header byte of each “outbound” idle cell.
Register is set to 0x00 when transmitting standard idle cell pattern.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
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