TABLE 8:
參數(shù)資料
型號(hào)： XRT72L71IQ
廠商： Exar Corporation
文件頁(yè)數(shù)： 54/102頁(yè)
文件大?。?/td> 0K
描述： IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告： XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝： 24
控制器類型： DS3 ATM UNI，透明通道調(diào)幀器
電源電壓： 3.3V
電流 - 電源： 120mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
51
TABLE 8: TEST CELL ERROR ACCUMULATOR HOLDING REGISTER
REGISTER 7
TEST CELL ERROR ACCUMULATOR HOLDING REGISTER
HEX ADDRESS: 0X07
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
TEST CELL HOLDING
REGISTER
RO
0x00
Holds the “Unread” byte of the 16-bit Test Cell Error Accumulator, when that
register is read. The XRT72L71 will transfer the contents of the “Unread”
byte to this “Holding” register, anytime the Bidirectional Data Bus (of the
Microprocessor Interface) is configured to be 8-bits wide.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 9: TEST CELL HEADER BYTE-1
REGISTER 8
TEST CELL HEADER BYTE-1
HEX ADDRESS: 0X08
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
TEST CELL HEADER
BYTE 1
R/W
0x11
Test Cell Header Byte - 1
Permits the user to define the value of “Header Byte # 1” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 10: TEST CELL HEADER BYTE-2
REGISTER 9
TEST CELL HEADER BYTE-2
HEX ADDRESS: 0X09
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
TEST CELL HEADER
BYTE 2
R/W
0x22
Test Cell Header Byte - 2
Permits the user to define the value of “Header Byte # 2” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 11: TEST CELL HEADER BYTE-3
REGISTER 10
TEST CELL HEADER BYTE-3
HEX ADDRESS: 0X0A
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
TEST CELL HEADER
BYTE 3
R/W
0x33
Test Cell Header Byte - 3
Permits the user to define the value of “Header Byte # 3” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 12: TEST CELL HEADER BYTE-4
REGISTER 11
TEST CELL HEADER BYTE-4
HEX ADDRESS: 0X0B
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
TEST CELL HEADER
BYTE 4
R/W
0x44
Test Cell Header Byte - 4
Permits the user to define the value of “Header Byte # 4” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
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