TABLE 32:
參數(shù)資料
型號(hào): XRT72L71IQ
廠商: Exar Corporation
文件頁(yè)數(shù): 68/102頁(yè)
文件大?。?/td> 0K
描述: IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告: XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝: 24
控制器類型: DS3 ATM UNI,透明通道調(diào)幀器
電源電壓: 3.3V
電流 - 電源: 120mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
包裝: 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
64
TABLE 32: TX DS3 LAPD STATUS/INTERRUPT REGISTER
REGISTER 31
TX DS3 LAPD STATUS/INTERRUPT REGISTER
HEX ADDRESS: 0X1F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-4
Unused
RO
0
3
Tx DL Start
R/W
0
0 to 1 transition configures the LAPD Transmitter to begin its transmission of
the PMDL (or LAPD Message) consisting of the data residing within the
“Transmit LAPD Message” buffer.
NOTE: This bit-field is only active if the XRT72L71 has been configured to
support the “C-bit Parity” Framing format.
2
Tx DL Busy
RO
0
0: LAPD Transmitter is NOT currently transmitting a LAPD Message to the
Remote Terminal Equipment; and is not available to transmit a new LAPD
Message.
1: LAPD Transmitter is currently transmitting a LAPD Message to the
Remote Terminal Equipment.
NOTE: This bit-field is only active if the XRT72L71 has been config-
ured to support the “C-bit Parity” Framing format.
1
Tx LAPD Interrupt Enable
R/W
0
0: “Completion of Transmission of LAPD Message” Interrupt is disabled.
1: “Completion of Transmission of LAPD Message” Interrupt is enabled. The
XRT72L71 will generate an interrupt, anytime the LAPD Transmitter has
completed its transmission of a given LAPD Message.
NOTE: This bit-field is only active if the XRT72L71 has been configured to
support the “C-bit Parity” Framing format.
0
Tx LAPD Interrupt Status
RUR
0
0: “Completion of Transmission of LAPD Message” interrupt has NOT
occurred since the last read of this register.
1: “Completion of Transmission of LAPD Message” interrupt has occurred
since the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 has been configured to
support the “C-bit Parity” Framing format.
TABLE 33: PMON LCV EVENT COUNT REGISTER - MSB
REGISTER 32
PMON LCV EVENT COUNT REGISTER - MSB
HEX ADDRESS: 0X20
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
LCV Count High byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON LCV Event Count Reg-
ister - LSB” contains the 16-bit value for the total number of Line Code Viola-
tions that have been detected since the last read of this register.
This register contains the “High” Byte of this 16-bit expression.
NOTE: This register is only active if the “B3ZS Decoder” (within the
XRT72L71) has been enabled.
TABLE 34: PMON LCV EVENT COUNT REGISTER - LSB
REGISTER 33
PMON LCV EVENT COUNT REGISTER - LSB
HEX ADDRESS: 0X21
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
LCV Count Low byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON LCV Event Count Reg-
ister - MSB” contains the 16 bit value for the total number of Line Code Viola-
tions that have been detected since the last read of this register.
This register contains the “Low” Byte of this 16-bit expression.
NOTE: This register is only active if the “B3ZS Decoder” (within the
XRT72L71) has been enabled.
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