TABLE 52:
參數(shù)資料
型號: XRT72L71IQ
廠商: Exar Corporation
文件頁數(shù): 74/102頁
文件大?。?/td> 0K
描述: IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告: XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝: 24
控制器類型: DS3 ATM UNI,透明通道調(diào)幀器
電源電壓: 3.3V
電流 - 電源: 120mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
包裝: 托盤
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
69
TABLE 52: PMON RECEIVED IDLE CELL COUNT/PRBS ERROR COUNT - LSB
REGISTER 51
PMON RECEIVED IDLE CELL COUNT/PRBS ERROR COUNT - LSB
HEX ADDRESS: 0X33
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Rx Idle Cell Count Low-
byte/
PRBS Error Count Low-
byte
RUR
0x00
ATM Mode: This register, along with “PMON Received Idle Cell
Count - MSB” contains the 16 bit value for the total number of idle
cells that have been received by the Receive Cell Processor, since
the last read of this register. This register contains the “Low” byte
value of this 16-bit expression.
Clear Channel Framer Mode: This register, along with “PMON
PRBS Error Count - MSB” regster contains the 16 bit value for the
total number of PRBS bit errors that have been received (by the
PRBS Receiver) since the last read of this register. This register
contains the “Low” byte value of this 16-bit expression.
TABLE 53: PMON RECEIVE VALID CELL COUNT - MSB
REGISTER 52
PMON RECEIVE VALID CELL COUNT - MSB
HEX ADDRESS: 0X34
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Rx Valid Cell Count High-
byte
RUR
0x00
This Reset-upon-Read register, along with PMON Receive Valid Cell Count -
LSB” contains the 16 bit value for the total number of Valid Cells that have
been received since the last read of this register. This register contains the
“High” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 54: PMON RECEIVE VALID CELL COUNT - LSB
REGISTER 53
PMON RECEIVE VALID CELL COUNT - LSB
HEX ADDRESS: 0X35
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Rx Valid Cell Count Low-
byte
RUR
0x00
This Reset-upon-Read register, along with PMON Receive Valid Cell Count -
MSB” contains the 16 bit value for the total number of Valid Cells that have
been received since the last read of this register. This register contains the
“Low” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 55: PMON DISCARDED CELL COUNT - MSB
REGISTER 54
PMON DISCARDED CELL COUNT - MSB
HEX ADDRESS: 0X36
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Cell Drop Count High-byte
RUR
0x00
This Reset-upon-Read register, along with PMON Discarded Cell Count -
LSB” contains the 16 bit value for the total number of cells that have been
discarded since the last read of this register. This register contains the
“High” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
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