TABLE 71:
參數(shù)資料
型號: XRT72L71IQ
廠商: Exar Corporation
文件頁數(shù): 79/102頁
文件大?。?/td> 0K
描述: IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告: XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝: 24
控制器類型: DS3 ATM UNI,透明通道調(diào)幀器
電源電壓: 3.3V
電流 - 電源: 120mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
包裝: 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
74
TABLE 71: RX PLCP INTERRUPT STATUS REGISTER
REGISTER 70
RX PLCP INTERRUPT STATUS REGISTER
HEX ADDRESS: 0X46
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-2
Unused
RO
0
1
POOF Interrupt Status
RUR
0
0: Indicates that the “Change in POOF Condition” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Change in POOF Condition” interrupt has occurred
since the last read of this register.
NOTE: This bit-field is only active if the XRT72L71is operating in both the
“ATM UNI” and the “PLCP” Modes.
0
PLOF Interrupt Status
RUR
0
0: Indicates that the “Change in PLOF Condition” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Change in PLOF Condition” interrupt has occurred
since the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
TABLE 72: FUTURE USE
REGISTER 71
FUTURE USE
HEX ADDRESS: 0X47
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
TABLE 73: TX PLCP FA1 BYTE ERROR MASK REGISTER
REGISTER 72
TX PLCP FA1 BYTE ERROR MASK REGISTER
HEX ADDRESS: 0X48
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
FA1 Error Mask
R/W
0x00
The Transmit PLCP Processor block always XORs contents of this register
with the contents of the FA1 byte (within a PLCP frame). This “XORed” value
is then written back into the “FA1” byte field, within each “outbound” PLCP
Frame; prior to transmission. Setting any of these bit-fields to “1” introduces
error in that specific bit, within each “outbound” FA1 byte.
Register must be set to 0x00 for normal operation,
NOTE: This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
TABLE 74: TX PLCP FA2 BYTE ERROR MASK REGISTER
REGISTER 73
TX PLCP FA2 BYTE ERROR MASK REGISTER
HEX ADDRESS: 0X49
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
FA2 Error Mask
R/W
0x00
The Transmit PLCP Processor block always XORs contents of this register
with the contents of the FA2 byte (within a PLCP frame). This “XORed” value
is then written back into the “FA1” byte field, within each “outbound” PLCP
Frame; prior to transmission. Setting any of these bit-fields to “1” introduces
error in that specific bit, within each “outbound” FA1 byte.
Register must be set to 0x00 for normal operation,
NOTE: This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
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