XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
70
TABLE 56: PMON DISCARDED CELL COUNT - LSB
REGISTER 55
PMON DISCARDED CELL COUNT - LSB
HEX ADDRESS: 0X37
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Cell Drop Count Low-byte
RUR
0x00
This Reset-upon-Read register, along with PMON Discarded Cell Count -
MSB” contains the 16 bit value for the total number of cells that have been
discarded since the last read of this register. This register contains the “Low”
byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 57: PMON TRANSMIT IDLE CELL COUNT - MSB
REGISTER 56
PMON TRANSMIT IDLE CELL COUNT - MSB
HEX ADDRESS: 0X38
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Count High-
byte
RUR
0x00
This Reset-upon-Read register, along with PMON Transmit Idle Cell Count -
LSB contains the 16 bit value for the total number of Idle cells that have been
trnasmitted by the Transmit Cell Processor, since the last read of this regis-
ter. This register contains the “High” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 58: PMON TRANSMIT IDLE CELL COUNT - LSB
REGISTER 57
PMON TRANSMIT IDLE CELL COUNT - LSB
HEX ADDRESS: 0X39
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Count Low-
byte
RUR
0x00
This Reset-upon-Read register, along with PMON Transmit Idle Cell Count -
MSB contains the 16 bit value for the total number of Idle cells that have
been trnasmitted by the Transmit Cell Processor, since the last read of this
register. This register contains the “Low” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 59: PMON TRANSMIT VALID CELL COUNT - MSB
REGISTER 58
PMON TRANSMIT VALID CELL COUNT - MSB
HEX ADDRESS: 0X3A
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Valid Cell Count High-
byte
RUR
0x00
This Reset-upon-Read register, along with PMON Transmit Valid Cell Count -
LSB contains the 16 bit value for the total number of Valid cells that have
been trnasmitted by the Transmit Cell Processor, since the last read of this
register. This register contains the “High” byte value of this 16-bit expres-
sion.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.