TABLE 80:
參數(shù)資料
型號(hào)： XRT72L71IQ
廠商： Exar Corporation
文件頁數(shù)： 85/102頁
文件大?。?/td> 0K
描述： IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告： XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝： 24
控制器類型： DS3 ATM UNI，透明通道調(diào)幀器
電源電壓： 3.3V
電流 - 電源： 120mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
79
TABLE 80: RX CP INTERRUPT STATUS REGISTER
REGISTER 79
RX CP INTERRUPT STATUS REGISTER
HEX ADDRESS: 0X4F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
RUR
0
0: Receive OAM Cell Buffer/FIFO has not experienced an “Overrun” event
since the last read of this register.
1: Receive OAM Cell Buffer/FIFO has experienced an “Overrun” event since
the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
6-3
Unused
RO
0
2
OAM Interrupt Status/
OAM Cell Pending
RUR/RO
0
OAM FIFO mode:
0: Indicates that the “Receive OAM Cell FIFO” is empty and does not con-
tain any new OAM cell data.
1: Indicates that there at least one unread OAM cell exists within the
“Receive OAM Cell FIFO”.
NOTE: If the “Receive OAM Cell” Buffer/FIFO is configured to operate in the
“FIFO” Mode, then this bit-field is “Read-Only”.
OAM Buffer Mode:
0: Indicates that the “Receipt of OAM Cell” Interrupt has NOT occurred since
the last read of this register.
1: Indicates that the “Receipt of OAM Cell” Interrupt has occurred since the
last read of this register.
1
LCD Interrupt Status
RUR
0
0: Indicates that the “Change in LCD Condition” interrupt has NOT occurred
since the last read of this register.
1: Indicates that the “Change in LCD Condition” Interrupt has occurred since
the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
0
HEC Byte Error Interrupt
Status
RUR
0
0: Indicates that the “Detection of HEC Byte” Error has NOT occurred since
the last read of this register.
1: Indicates that the “Detection of HEC Byte” Error has occurred since the
last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
TABLE 81: RX CP IDLE CELL PATTERN HEADER BYTE-1
REGISTER 80
RX CP IDLE CELL PATTERN HEADER BYTE-1
HEX ADDRESS: 0X50
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Rx Idle Cell Pattern 1
R/W
0x00
This register (along with the “Rx Idle Cell Mask 1” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 1.
NOTES:
1. This register should be set to “0x00” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
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