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參數(shù)資料
| 型號： | XRT72L71IQ |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 91/102頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER DS3 ATM UNI 160PQFP |
| 產(chǎn)品變化通告： | XRT72Lx Series Obsolescence 02/May/2012 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 控制器類型： | DS3 ATM UNI，透明通道調(diào)幀器 |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 120mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
85
TABLE 97: TX CP CONTROL REGISTER
REGISTER 96
TX CP CONTROL REGISTER
HEX ADDRESS: 0X60
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Scrambler Enable
R/W
1
0: Disables scrambling of payload bits
1: Enables scrambling of payload bits
6
Coset Enable
R/W
1
0: Disables addition of Coset Polynomial to HEC byte
1: Enables addition of Coset Polynomial to HEC byte
5
Valid Cell HEC Insert
Enable
R/W
1
0: HEC Byte Calculation and Insertion is disabled. Hence, no modification is
performed on the 5th octet within each “outbound” valid ATM cell.
1: HEC Byte Calculation and Insertion are enabled.
NOTES:
1. This register bit-field only applies to Valid (e.g., User and OAM)
cells.
2. This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” mode.
4
TDP Check Pattern
R/W
1
0: An Alternating 0x55/0xAA pattern is expected (as the “Data Path Integrity
Check byte) in the fifth octet position, within each Valid cell that is processed
by the Transmit Cell Processor.
1: A constant 0x55 pattern is expected (as the “Data Path Integrity Check”
byte) in the fifth octet position, within each Valid cell that is processed by the
Transmit Cell Processor.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
3
GFC Insert Enable
R/W
0
0: The “GFC Input Port” is disabled.
1: The “GFC Input Port” is enabled. Data is read via TxGFC serial input pin
and is inserted into GFC nibble-field within of each “outbound” ATM cell.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
2
TDP Error Interrupt Enable
R/w
0
0: Disables the “Data Path Integrity Check” interrupt.
1: Enables the “Data Path Integrity Check” interrupt.
1
Idle Cell HEC Insert Enable
R/w
1
0: HEC Byte Calculation and Insertion is disabled. Hence, no modification is
performed on the 5th octet within each “outbound” Idle ATM cell.
1: HEC Byte Calculation and Insertion are enabled.
NOTES:
1. This register bit-field only applies to Idle cells.
2. This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” mode.
0
TDP Error Interrupt Status
RUR
0
0: Indicates that the “Data Path Integrity Check” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Data Path Integrity Check” Interrupt has occurred since
the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is configured to
operate in the “ATM UNI” Mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT72L71IQ-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single CH DS3 UNI (3.3V) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT72L73IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT7300 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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